operands.isa (7796:9bd6b37d0189) | operands.isa (7797:998b217dcae7) |
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1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 66 unchanged lines hidden (view full) --- 75 setNextPC(xc, %(final_val)s); 76 } else { 77 setIWNextPC(xc, %(final_val)s); 78 } 79 } else { 80 xc->%(func)s(this, %(op_idx)s, %(final_val)s); 81 } 82 ''' | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 66 unchanged lines hidden (view full) --- 75 setNextPC(xc, %(final_val)s); 76 } else { 77 setIWNextPC(xc, %(final_val)s); 78 } 79 } else { 80 xc->%(func)s(this, %(op_idx)s, %(final_val)s); 81 } 82 ''' |
83 84 #PCState operands need to have a sorting index (the number at the end) 85 #less than all the integer registers which might update the PC. That way 86 #if the flag bits of the pc state are updated and a branch happens through 87 #R15, the updates are layered properly and the R15 update isn't lost. 88 srtNormal = 5 89 srtCpsr = 4 90 srtBase = 3 91 srtPC = 2 92 srtMode = 1 93 srtEPC = 0 94 95 def floatReg(idx): 96 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal) 97 98 def intReg(idx): 99 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 100 maybePCRead, maybePCWrite) 101 102 def intRegNPC(idx): 103 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal) 104 105 def intRegAPC(idx, id = srtNormal): 106 return ('IntReg', 'uw', idx, 'IsInteger', id, 107 maybeAlignedPCRead, maybePCWrite) 108 109 def intRegIWPC(idx): 110 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 111 maybePCRead, maybeIWPCWrite) 112 113 def intRegAIWPC(idx): 114 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 115 maybePCRead, maybeAIWPCWrite) 116 117 def intRegCC(idx): 118 return ('IntReg', 'uw', idx, None, srtNormal) 119 120 def cntrlReg(idx, id = srtNormal, type = 'uw'): 121 return ('ControlReg', type, idx, (None, None, 'IsControl'), id) 122 123 def cntrlRegNC(idx, id = srtNormal, type = 'uw'): 124 return ('ControlReg', type, idx, None, id) 125 126 def pcStateReg(idx, id): 127 return ('PCState', 'uw', idx, (None, None, 'IsControl'), id) |
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83}}; 84 85def operands {{ 86 #Abstracted integer reg operands | 128}}; 129 130def operands {{ 131 #Abstracted integer reg operands |
87 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 3, 88 maybePCRead, maybePCWrite), 89 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3), 90 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3), 91 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 3), 92 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 3), 93 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 3), 94 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 3), 95 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 3), 96 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 3), 97 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 3), 98 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 3), 99 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 3), 100 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 3), 101 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 3), 102 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 3), 103 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 3), 104 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 3), 105 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 3), 106 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 3, 107 maybePCRead, maybePCWrite), 108 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 3, 109 maybePCRead, maybePCWrite), 110 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3), 111 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3), 112 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 3), 113 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 3), 114 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 3), 115 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3, 116 maybePCRead, maybeIWPCWrite), 117 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3, 118 maybePCRead, maybeAIWPCWrite), 119 'SpMode': ('IntReg', 'uw', 120 'intRegInMode((OperatingMode)regMode, INTREG_SP)', 121 'IsInteger', 3), 122 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 3), 123 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, 124 maybeAlignedPCRead, maybePCWrite), 125 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 3, 126 maybePCRead, maybePCWrite), 127 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, 128 maybePCRead, maybePCWrite), 129 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3), 130 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3), 131 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 3), 132 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 3), 133 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 3), 134 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 3), 135 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 3), 136 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 3), 137 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 3), 138 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 3), 139 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 3), 140 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 3), 141 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 3), 142 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 3), 143 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 3), 144 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 3), 145 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 3), 146 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 3), 147 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 3, 148 maybePCRead, maybePCWrite), 149 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3), 150 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3), 151 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 3), 152 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 3), 153 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 3), 154 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 3, 155 maybePCRead, maybePCWrite), 156 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 3, 157 maybePCRead, maybePCWrite), 158 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 3, 159 maybePCRead, maybePCWrite), 160 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 3, 161 maybePCRead, maybePCWrite), 162 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 3, 163 maybePCRead, maybePCWrite), 164 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 3, 165 maybePCRead, maybePCWrite), 166 #General Purpose Integer Reg Operands 167 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 3, maybePCRead, maybePCWrite), 168 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 3, maybePCRead, maybePCWrite), 169 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 170 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite), 171 'R7': ('IntReg', 'uw', '7', 'IsInteger', 3), 172 'R0': ('IntReg', 'uw', '0', 'IsInteger', 3), 173 'R1': ('IntReg', 'uw', '0', 'IsInteger', 3), 174 'R2': ('IntReg', 'uw', '1', 'IsInteger', 3), 175 'Rt' : ('IntReg', 'uw', 'RT', 'IsInteger', 3, maybePCRead, maybePCWrite), | 132 'Dest': intReg('dest'), 133 'IWDest': intRegIWPC('dest'), 134 'AIWDest': intRegAIWPC('dest'), 135 'Dest2': intReg('dest2'), 136 'Result': intReg('result'), 137 'Base': intRegAPC('base', id = srtBase), 138 'Index': intReg('index'), 139 'Shift': intReg('shift'), 140 'Op1': intReg('op1'), 141 'Op2': intReg('op2'), 142 'Op3': intReg('op3'), 143 'Reg0': intReg('reg0'), 144 'Reg1': intReg('reg1'), 145 'Reg2': intReg('reg2'), 146 'Reg3': intReg('reg3'), |
176 | 147 |
177 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3), 178 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3), 179 'OptCondCodes': ('IntReg', 'uw', | 148 #Fixed index integer reg operands 149 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'), 150 'LR': intRegNPC('INTREG_LR'), 151 'R7': intRegNPC('7'), 152 'R0': intRegNPC('0'), 153 'R1': intRegNPC('0'), 154 'R2': intRegNPC('1'), 155 156 #Pseudo integer condition code registers 157 'CondCodes': intRegCC('INTREG_CONDCODES'), 158 'OptCondCodes': intRegCC( |
180 '''(condCode == COND_AL || condCode == COND_UC) ? | 159 '''(condCode == COND_AL || condCode == COND_UC) ? |
181 INTREG_ZERO : INTREG_CONDCODES''', None, 3), 182 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 3), | 160 INTREG_ZERO : INTREG_CONDCODES'''), 161 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), |
183 | 162 |
163 #Abstracted floating point reg operands 164 'FpDest': floatReg('(dest + 0)'), 165 'FpDestP0': floatReg('(dest + 0)'), 166 'FpDestP1': floatReg('(dest + 1)'), 167 'FpDestP2': floatReg('(dest + 2)'), 168 'FpDestP3': floatReg('(dest + 3)'), 169 'FpDestP4': floatReg('(dest + 4)'), 170 'FpDestP5': floatReg('(dest + 5)'), 171 'FpDestP6': floatReg('(dest + 6)'), 172 'FpDestP7': floatReg('(dest + 7)'), 173 'FpDestS0P0': floatReg('(dest + step * 0 + 0)'), 174 'FpDestS0P1': floatReg('(dest + step * 0 + 1)'), 175 'FpDestS1P0': floatReg('(dest + step * 1 + 0)'), 176 'FpDestS1P1': floatReg('(dest + step * 1 + 1)'), 177 'FpDestS2P0': floatReg('(dest + step * 2 + 0)'), 178 'FpDestS2P1': floatReg('(dest + step * 2 + 1)'), 179 'FpDestS3P0': floatReg('(dest + step * 3 + 0)'), 180 'FpDestS3P1': floatReg('(dest + step * 3 + 1)'), 181 182 'FpDest2': floatReg('(dest2 + 0)'), 183 'FpDest2P0': floatReg('(dest2 + 0)'), 184 'FpDest2P1': floatReg('(dest2 + 1)'), 185 'FpDest2P2': floatReg('(dest2 + 2)'), 186 'FpDest2P3': floatReg('(dest2 + 3)'), 187 188 'FpOp1': floatReg('(op1 + 0)'), 189 'FpOp1P0': floatReg('(op1 + 0)'), 190 'FpOp1P1': floatReg('(op1 + 1)'), 191 'FpOp1P2': floatReg('(op1 + 2)'), 192 'FpOp1P3': floatReg('(op1 + 3)'), 193 'FpOp1P4': floatReg('(op1 + 4)'), 194 'FpOp1P5': floatReg('(op1 + 5)'), 195 'FpOp1P6': floatReg('(op1 + 6)'), 196 'FpOp1P7': floatReg('(op1 + 7)'), 197 'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'), 198 'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'), 199 'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'), 200 'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'), 201 'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'), 202 'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'), 203 'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'), 204 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'), 205 206 'FpOp2': floatReg('(op2 + 0)'), 207 'FpOp2P0': floatReg('(op2 + 0)'), 208 'FpOp2P1': floatReg('(op2 + 1)'), 209 'FpOp2P2': floatReg('(op2 + 2)'), 210 'FpOp2P3': floatReg('(op2 + 3)'), 211 212 #Abstracted control reg operands 213 'MiscDest': cntrlReg('dest'), 214 'MiscOp1': cntrlReg('op1'), 215 216 #Fixed index control regs 217 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), 218 'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'), 219 'Spsr': cntrlRegNC('MISCREG_SPSR'), 220 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 221 'Fpsid': cntrlRegNC('MISCREG_FPSID'), 222 'Fpscr': cntrlRegNC('MISCREG_FPSCR'), 223 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'), 224 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'), 225 'Cpacr': cntrlReg('MISCREG_CPACR'), 226 'Fpexc': cntrlRegNC('MISCREG_FPEXC'), 227 'Sctlr': cntrlRegNC('MISCREG_SCTLR'), 228 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'), 229 |
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184 #Register fields for microops | 230 #Register fields for microops |
185 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybePCWrite), 186 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, 187 maybePCRead, maybeIWPCWrite), 188 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 3), 189 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 3, maybePCRead, maybePCWrite), 190 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 3, maybePCRead, maybePCWrite), | 231 'Ra' : intReg('ura'), 232 'IWRa' : intRegIWPC('ura'), 233 'Fa' : floatReg('ura'), 234 'Rb' : intReg('urb'), 235 'Rc' : intReg('urc'), |
191 192 #Memory Operand | 236 237 #Memory Operand |
193 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3), | 238 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), |
194 | 239 |
195 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2), 196 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3), 197 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3), 198 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3), 199 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3), 200 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3), 201 'FpscrQc': ('ControlReg', 'uw', 'MISCREG_FPSCR_QC', None, 3), 202 'FpscrExc': ('ControlReg', 'uw', 'MISCREG_FPSCR_EXC', None, 3), 203 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3), 204 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3), 205 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3), 206 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 3), 207 #PCS needs to have a sorting index (the number at the end) less than all 208 #the integer registers which might update the PC. That way if the flag 209 #bits of the pc state are updated and a branch happens through R15, the 210 #updates are layered properly and the R15 update isn't lost. 211 'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 0) | 240 #PCState fields 241 'PC': pcStateReg('instPC', srtPC), 242 'NPC': pcStateReg('instNPC', srtPC), 243 'pNPC': pcStateReg('instNPC', srtEPC), 244 'IWNPC': pcStateReg('instIWNPC', srtPC), 245 'Thumb': pcStateReg('thumb', srtPC), 246 'NextThumb': pcStateReg('nextThumb', srtMode), 247 'NextJazelle': pcStateReg('nextJazelle', srtMode), 248 249 #Register operands depending on a field in the instruction encoding. These 250 #should be avoided since they may not be portable across different 251 #encodings of the same instruction. 252 'Rd': intReg('RD'), 253 'Rm': intReg('RM'), 254 'Rs': intReg('RS'), 255 'Rn': intReg('RN'), 256 'Rt': intReg('RT') |
212}}; | 257}}; |