operands.isa (7260:4e15b9b23abe) | operands.isa (7279:157b02cc0ba1) |
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1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 76 unchanged lines hidden (view full) --- 85 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 86 forceNPC = 'xc->setNextPC(%(final_val)s)' 87}}; 88 89def operands {{ 90 #Abstracted integer reg operands 91 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 92 maybePCRead, maybePCWrite), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 76 unchanged lines hidden (view full) --- 85 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 86 forceNPC = 'xc->setNextPC(%(final_val)s)' 87}}; 88 89def operands {{ 90 #Abstracted integer reg operands 91 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 92 maybePCRead, maybePCWrite), |
93 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 0, 94 maybePCRead, maybePCWrite), |
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93 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 94 maybePCRead, maybeIWPCWrite), 95 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 96 maybePCRead, maybeAIWPCWrite), 97 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0), 98 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, 99 maybeAlignedPCRead, maybePCWrite), 100 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, --- 18 unchanged lines hidden (view full) --- 119 #General Purpose Integer Reg Operands 120 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 121 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 122 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 123 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 124 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 125 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 126 | 95 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 96 maybePCRead, maybeIWPCWrite), 97 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 98 maybePCRead, maybeAIWPCWrite), 99 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0), 100 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, 101 maybeAlignedPCRead, maybePCWrite), 102 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, --- 18 unchanged lines hidden (view full) --- 121 #General Purpose Integer Reg Operands 122 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 123 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 124 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 125 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 126 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 127 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 128 |
127 #Destination register for load/store double instructions 128 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 129 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 130 | |
131 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 132 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 133 134 #Register fields for microops 135 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 136 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, 137 maybePCRead, maybeIWPCWrite), 138 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), --- 23 unchanged lines hidden --- | 129 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 130 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 131 132 #Register fields for microops 133 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 134 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, 135 maybePCRead, maybeIWPCWrite), 136 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), --- 23 unchanged lines hidden --- |