operands.isa (14106:293e3f4b1321) | operands.isa (14108:881e7d85baf7) |
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1// -*- mode:c++ -*- 2// Copyright (c) 2010-2014, 2016-2018 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43 'sb' : 'int8_t', 44 'ub' : 'uint8_t', 45 'sh' : 'int16_t', 46 'uh' : 'uint16_t', 47 'sw' : 'int32_t', 48 'uw' : 'uint32_t', 49 'sd' : 'int64_t', 50 'ud' : 'uint64_t', | 1// -*- mode:c++ -*- 2// Copyright (c) 2010-2014, 2016-2018 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43 'sb' : 'int8_t', 44 'ub' : 'uint8_t', 45 'sh' : 'int16_t', 46 'uh' : 'uint16_t', 47 'sw' : 'int32_t', 48 'uw' : 'uint32_t', 49 'sd' : 'int64_t', 50 'ud' : 'uint64_t', |
51 'sq' : '__int128_t', 52 'uq' : '__uint128_t', |
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51 'tud' : 'std::array<uint64_t, 2>', 52 'sf' : 'float', 53 'df' : 'double', 54 'vc' : 'ArmISA::VecRegContainer', 55 # For operations that are implemented as a template 56 'x' : 'TPElem', 57 'xs' : 'TPSElem', 58 'xd' : 'TPDElem', --- 645 unchanged lines hidden --- | 53 'tud' : 'std::array<uint64_t, 2>', 54 'sf' : 'float', 55 'df' : 'double', 56 'vc' : 'ArmISA::VecRegContainer', 57 # For operations that are implemented as a template 58 'x' : 'TPElem', 59 'xs' : 'TPSElem', 60 'xd' : 'TPDElem', --- 645 unchanged lines hidden --- |