1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : 'int8_t',
44 'ub' : 'uint8_t',
45 'sh' : 'int16_t',
46 'uh' : 'uint16_t',
47 'sw' : 'int32_t',
48 'uw' : 'uint32_t',
49 'ud' : 'uint64_t',
50 'tud' : 'Twin64_t',
51 'sf' : 'float',
52 'df' : 'double'
53}};
54
55let {{
56 maybePCRead = '''
57 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybeAlignedPCRead = '''
60 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
61 xc->%(func)s(this, %(op_idx)s))
62 '''
63 maybePCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67 maybeIWPCWrite = '''
68 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
69 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
70 '''
71 maybeAIWPCWrite = '''
72 if (%(reg_idx)s == PCReg) {
73 bool thumb = THUMB;
74 if (thumb) {
75 setNextPC(xc, %(final_val)s);
76 } else {
77 setIWNextPC(xc, %(final_val)s);
78 }
79 } else {
80 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
81 }
82 '''
83
84 #PCState operands need to have a sorting index (the number at the end)
85 #less than all the integer registers which might update the PC. That way
86 #if the flag bits of the pc state are updated and a branch happens through
87 #R15, the updates are layered properly and the R15 update isn't lost.
88 srtNormal = 5
89 srtCpsr = 4
90 srtBase = 3
91 srtPC = 2
92 srtMode = 1
93 srtEPC = 0
94
95 def floatReg(idx):
96 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
97
98 def intReg(idx):
99 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
100 maybePCRead, maybePCWrite)
101
102 def intRegNPC(idx):
103 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
104
105 def intRegAPC(idx, id = srtNormal):
106 return ('IntReg', 'uw', idx, 'IsInteger', id,
107 maybeAlignedPCRead, maybePCWrite)
108
109 def intRegIWPC(idx):
110 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
111 maybePCRead, maybeIWPCWrite)
112
113 def intRegAIWPC(idx):
114 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
115 maybePCRead, maybeAIWPCWrite)
116
117 def intRegCC(idx):
118 return ('IntReg', 'uw', idx, None, srtNormal)
119
120 def cntrlReg(idx, id = srtNormal, type = 'uw'):
121 return ('ControlReg', type, idx, None, id)
122
123 def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
124 return ('ControlReg', type, idx, None, id)
125
126 def pcStateReg(idx, id):
127 return ('PCState', 'uw', idx, (None, None, 'IsControl'), id)
128}};
129
130def operands {{
131 #Abstracted integer reg operands
132 'Dest': intReg('dest'),
133 'IWDest': intRegIWPC('dest'),
134 'AIWDest': intRegAIWPC('dest'),
135 'Dest2': intReg('dest2'),
136 'Result': intReg('result'),
137 'Base': intRegAPC('base', id = srtBase),
138 'Index': intReg('index'),
139 'Shift': intReg('shift'),
140 'Op1': intReg('op1'),
141 'Op2': intReg('op2'),
142 'Op3': intReg('op3'),
143 'Reg0': intReg('reg0'),
144 'Reg1': intReg('reg1'),
145 'Reg2': intReg('reg2'),
146 'Reg3': intReg('reg3'),
147
148 #Fixed index integer reg operands
149 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
150 'LR': intRegNPC('INTREG_LR'),
151 'R7': intRegNPC('7'),
152 # First four arguments are passed in registers
153 'R0': intRegNPC('0'),
154 'R1': intRegNPC('1'),
155 'R2': intRegNPC('2'),
156 'R3': intRegNPC('3'),
157
158 #Pseudo integer condition code registers
159 'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'),
160 'CondCodesC': intRegCC('INTREG_CONDCODES_C'),
161 'CondCodesV': intRegCC('INTREG_CONDCODES_V'),
162 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'),
163 'OptCondCodesNZ': intRegCC(
164 '''(condCode == COND_AL || condCode == COND_UC ||
165 condCode == COND_CC || condCode == COND_CS ||
166 condCode == COND_VS || condCode == COND_VC) ?
167 INTREG_ZERO : INTREG_CONDCODES_NZ'''),
168 'OptCondCodesC': intRegCC(
169 '''(condCode == COND_HI || condCode == COND_LS ||
170 condCode == COND_CS || condCode == COND_CC) ?
171 INTREG_CONDCODES_C : INTREG_ZERO'''),
172 'OptShiftRmCondCodesC': intRegCC(
173 '''(condCode == COND_HI || condCode == COND_LS ||
174 condCode == COND_CS || condCode == COND_CC ||
175 shiftType == ROR) ?
176 INTREG_CONDCODES_C : INTREG_ZERO'''),
177 'OptCondCodesV': intRegCC(
178 '''(condCode == COND_VS || condCode == COND_VC ||
179 condCode == COND_GE || condCode == COND_LT ||
180 condCode == COND_GT || condCode == COND_LE) ?
181 INTREG_CONDCODES_V : INTREG_ZERO'''),
182 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
183
184 #Abstracted floating point reg operands
185 'FpDest': floatReg('(dest + 0)'),
186 'FpDestP0': floatReg('(dest + 0)'),
187 'FpDestP1': floatReg('(dest + 1)'),
188 'FpDestP2': floatReg('(dest + 2)'),
189 'FpDestP3': floatReg('(dest + 3)'),
190 'FpDestP4': floatReg('(dest + 4)'),
191 'FpDestP5': floatReg('(dest + 5)'),
192 'FpDestP6': floatReg('(dest + 6)'),
193 'FpDestP7': floatReg('(dest + 7)'),
194 'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
195 'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
196 'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
197 'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
198 'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
199 'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
200 'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
201 'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
202
203 'FpDest2': floatReg('(dest2 + 0)'),
204 'FpDest2P0': floatReg('(dest2 + 0)'),
205 'FpDest2P1': floatReg('(dest2 + 1)'),
206 'FpDest2P2': floatReg('(dest2 + 2)'),
207 'FpDest2P3': floatReg('(dest2 + 3)'),
208
209 'FpOp1': floatReg('(op1 + 0)'),
210 'FpOp1P0': floatReg('(op1 + 0)'),
211 'FpOp1P1': floatReg('(op1 + 1)'),
212 'FpOp1P2': floatReg('(op1 + 2)'),
213 'FpOp1P3': floatReg('(op1 + 3)'),
214 'FpOp1P4': floatReg('(op1 + 4)'),
215 'FpOp1P5': floatReg('(op1 + 5)'),
216 'FpOp1P6': floatReg('(op1 + 6)'),
217 'FpOp1P7': floatReg('(op1 + 7)'),
218 'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
219 'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
220 'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
221 'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
222 'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
223 'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
224 'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
225 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
226
227 'FpOp2': floatReg('(op2 + 0)'),
228 'FpOp2P0': floatReg('(op2 + 0)'),
229 'FpOp2P1': floatReg('(op2 + 1)'),
230 'FpOp2P2': floatReg('(op2 + 2)'),
231 'FpOp2P3': floatReg('(op2 + 3)'),
232
233 #Abstracted control reg operands
234 'MiscDest': cntrlReg('dest'),
235 'MiscOp1': cntrlReg('op1'),
236
237 #Fixed index control regs
238 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
239 'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
240 'Spsr': cntrlRegNC('MISCREG_SPSR'),
241 'Fpsr': cntrlRegNC('MISCREG_FPSR'),
242 'Fpsid': cntrlRegNC('MISCREG_FPSID'),
243 'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
244 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
245 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
246 'Cpacr': cntrlReg('MISCREG_CPACR'),
247 'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
248 'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
249 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
250 'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
251
252 #Register fields for microops
253 'URa' : intReg('ura'),
254 'IWRa' : intRegIWPC('ura'),
255 'Fa' : floatReg('ura'),
256 'URb' : intReg('urb'),
257 'URc' : intReg('urc'),
258
259 #Memory Operand
260 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
261
262 #PCState fields
263 'PC': pcStateReg('instPC', srtPC),
264 'NPC': pcStateReg('instNPC', srtPC),
265 'pNPC': pcStateReg('instNPC', srtEPC),
266 'IWNPC': pcStateReg('instIWNPC', srtPC),
267 'Thumb': pcStateReg('thumb', srtPC),
268 'NextThumb': pcStateReg('nextThumb', srtMode),
269 'NextJazelle': pcStateReg('nextJazelle', srtMode),
270 'NextItState': pcStateReg('nextItstate', srtMode),
271 'Itstate': pcStateReg('itstate', srtMode),
272
273 #Register operands depending on a field in the instruction encoding. These
274 #should be avoided since they may not be portable across different
275 #encodings of the same instruction.
276 'Rd': intReg('RD'),
277 'Rm': intReg('RM'),
278 'Rs': intReg('RS'),
279 'Rn': intReg('RN'),
280 'Rt': intReg('RT')
281}};