1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated

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75 setNextPC(xc, %(final_val)s);
76 } else {
77 setIWNextPC(xc, %(final_val)s);
78 }
79 } else {
80 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
81 }
82 '''
83
84 #PCState operands need to have a sorting index (the number at the end)
85 #less than all the integer registers which might update the PC. That way
86 #if the flag bits of the pc state are updated and a branch happens through
87 #R15, the updates are layered properly and the R15 update isn't lost.
88 srtNormal = 5
89 srtCpsr = 4
90 srtBase = 3
91 srtPC = 2
92 srtMode = 1
93 srtEPC = 0
94
95 def floatReg(idx):
96 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
97
98 def intReg(idx):
99 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
100 maybePCRead, maybePCWrite)
101
102 def intRegNPC(idx):
103 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
104
105 def intRegAPC(idx, id = srtNormal):
106 return ('IntReg', 'uw', idx, 'IsInteger', id,
107 maybeAlignedPCRead, maybePCWrite)
108
109 def intRegIWPC(idx):

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115 maybePCRead, maybeAIWPCWrite)
116
117 def intRegCC(idx):
118 return ('IntReg', 'uw', idx, None, srtNormal)
119
120 def cntrlReg(idx, id = srtNormal, type = 'uw'):
121 return ('ControlReg', type, idx, None, id)
122
123 def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
124 return ('ControlReg', type, idx, None, id)
125
126 def pcStateReg(idx, id):
127 return ('PCState', 'uw', idx, (None, None, 'IsControl'), id)
128}};
129
130def operands {{
131 #Abstracted integer reg operands
132 'Dest': intReg('dest'),
133 'IWDest': intRegIWPC('dest'),
134 'AIWDest': intRegAIWPC('dest'),
135 'Dest2': intReg('dest2'),
136 'Result': intReg('result'),
137 'Base': intRegAPC('base', id = srtBase),
138 'Index': intReg('index'),
139 'Shift': intReg('shift'),
140 'Op1': intReg('op1'),
141 'Op2': intReg('op2'),
142 'Op3': intReg('op3'),
143 'Reg0': intReg('reg0'),
144 'Reg1': intReg('reg1'),
145 'Reg2': intReg('reg2'),
146 'Reg3': intReg('reg3'),
147
148 #Fixed index integer reg operands
149 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
150 'LR': intRegNPC('INTREG_LR'),
151 'R7': intRegNPC('7'),
152 # First four arguments are passed in registers
153 'R0': intRegNPC('0'),
154 'R1': intRegNPC('1'),
155 'R2': intRegNPC('2'),
156 'R3': intRegNPC('3'),
157
158 #Pseudo integer condition code registers
159 'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'),
160 'CondCodesC': intRegCC('INTREG_CONDCODES_C'),
161 'CondCodesV': intRegCC('INTREG_CONDCODES_V'),
162 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'),
163 'OptCondCodesNZ': intRegCC(
164 '''(condCode == COND_AL || condCode == COND_UC ||

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225 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
226
227 'FpOp2': floatReg('(op2 + 0)'),
228 'FpOp2P0': floatReg('(op2 + 0)'),
229 'FpOp2P1': floatReg('(op2 + 1)'),
230 'FpOp2P2': floatReg('(op2 + 2)'),
231 'FpOp2P3': floatReg('(op2 + 3)'),
232
233 #Abstracted control reg operands
234 'MiscDest': cntrlReg('dest'),
235 'MiscOp1': cntrlReg('op1'),
236
237 #Fixed index control regs
238 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
239 'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
240 'Spsr': cntrlRegNC('MISCREG_SPSR'),
241 'Fpsr': cntrlRegNC('MISCREG_FPSR'),
242 'Fpsid': cntrlRegNC('MISCREG_FPSID'),
243 'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
244 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
245 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
246 'Cpacr': cntrlReg('MISCREG_CPACR'),
247 'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
248 'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
249 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
250 'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
251
252 #Register fields for microops
253 'URa' : intReg('ura'),
254 'IWRa' : intRegIWPC('ura'),
255 'Fa' : floatReg('ura'),
256 'URb' : intReg('urb'),
257 'URc' : intReg('urc'),
258
259 #Memory Operand
260 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
261
262 #PCState fields
263 'PC': pcStateReg('instPC', srtPC),
264 'NPC': pcStateReg('instNPC', srtPC),
265 'pNPC': pcStateReg('instNPC', srtEPC),
266 'IWNPC': pcStateReg('instIWNPC', srtPC),
267 'Thumb': pcStateReg('thumb', srtPC),
268 'NextThumb': pcStateReg('nextThumb', srtMode),
269 'NextJazelle': pcStateReg('nextJazelle', srtMode),
270 'NextItState': pcStateReg('nextItstate', srtMode),
271 'Itstate': pcStateReg('itstate', srtMode),
272
273 #Register operands depending on a field in the instruction encoding. These
274 #should be avoided since they may not be portable across different
275 #encodings of the same instruction.
276 'Rd': intReg('RD'),
277 'Rm': intReg('RM'),
278 'Rs': intReg('RS'),
279 'Rn': intReg('RN'),
280 'Rt': intReg('RT')
281}};