1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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94 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
95 maybePCRead, maybePCWrite),
96 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
97 maybePCRead, maybePCWrite),
98 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
99 maybePCRead, maybeIWPCWrite),
100 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
101 maybePCRead, maybeAIWPCWrite),
102 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
103 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
104 maybeAlignedPCRead, maybePCWrite),
105 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
106 maybePCRead, maybePCWrite),
107 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
108 maybePCRead, maybePCWrite),
109 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),

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