1// -*- mode:c++ -*-
2// Copyright (c) 2010-2014 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated

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44 'ub' : 'uint8_t',
45 'sh' : 'int16_t',
46 'uh' : 'uint16_t',
47 'sw' : 'int32_t',
48 'uw' : 'uint32_t',
49 'ud' : 'uint64_t',
50 'tud' : 'Twin64_t',
51 'sf' : 'float',
52 'df' : 'double'
53}};
54
55let {{
56 maybePCRead = '''
57 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybeAlignedPCRead = '''
60 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :

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112 #R15, the updates are layered properly and the R15 update isn't lost.
113 srtNormal = 5
114 srtCpsr = 4
115 srtBase = 3
116 srtPC = 2
117 srtMode = 1
118 srtEPC = 0
119
120 def floatReg(idx):
121 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
122
123 def intReg(idx):
124 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
125 maybePCRead, maybePCWrite)
126
127 def intReg64(idx):

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292
293 'FpOp2': floatReg('(op2 + 0)'),
294 'FpOp2P0': floatReg('(op2 + 0)'),
295 'FpOp2P1': floatReg('(op2 + 1)'),
296 'FpOp2P2': floatReg('(op2 + 2)'),
297 'FpOp2P3': floatReg('(op2 + 3)'),
298
299 # Create AArch64 unpacked view of the FP registers
300 'AA64FpOp1P0': floatReg('((op1 * 4) + 0)'),
301 'AA64FpOp1P1': floatReg('((op1 * 4) + 1)'),
302 'AA64FpOp1P2': floatReg('((op1 * 4) + 2)'),
303 'AA64FpOp1P3': floatReg('((op1 * 4) + 3)'),
304 'AA64FpOp2P0': floatReg('((op2 * 4) + 0)'),
305 'AA64FpOp2P1': floatReg('((op2 * 4) + 1)'),
306 'AA64FpOp2P2': floatReg('((op2 * 4) + 2)'),
307 'AA64FpOp2P3': floatReg('((op2 * 4) + 3)'),
308 'AA64FpOp3P0': floatReg('((op3 * 4) + 0)'),
309 'AA64FpOp3P1': floatReg('((op3 * 4) + 1)'),
310 'AA64FpOp3P2': floatReg('((op3 * 4) + 2)'),
311 'AA64FpOp3P3': floatReg('((op3 * 4) + 3)'),
312 'AA64FpDestP0': floatReg('((dest * 4) + 0)'),
313 'AA64FpDestP1': floatReg('((dest * 4) + 1)'),
314 'AA64FpDestP2': floatReg('((dest * 4) + 2)'),
315 'AA64FpDestP3': floatReg('((dest * 4) + 3)'),
316 'AA64FpDest2P0': floatReg('((dest2 * 4) + 0)'),
317 'AA64FpDest2P1': floatReg('((dest2 * 4) + 1)'),
318 'AA64FpDest2P2': floatReg('((dest2 * 4) + 2)'),
319 'AA64FpDest2P3': floatReg('((dest2 * 4) + 3)'),
320
321 'AA64FpOp1P0V0': floatReg('((((op1+0)) * 4) + 0)'),
322 'AA64FpOp1P1V0': floatReg('((((op1+0)) * 4) + 1)'),
323 'AA64FpOp1P2V0': floatReg('((((op1+0)) * 4) + 2)'),
324 'AA64FpOp1P3V0': floatReg('((((op1+0)) * 4) + 3)'),
325
326 'AA64FpOp1P0V1': floatReg('((((op1+1)) * 4) + 0)'),
327 'AA64FpOp1P1V1': floatReg('((((op1+1)) * 4) + 1)'),
328 'AA64FpOp1P2V1': floatReg('((((op1+1)) * 4) + 2)'),
329 'AA64FpOp1P3V1': floatReg('((((op1+1)) * 4) + 3)'),
330
331 'AA64FpOp1P0V2': floatReg('((((op1+2)) * 4) + 0)'),
332 'AA64FpOp1P1V2': floatReg('((((op1+2)) * 4) + 1)'),
333 'AA64FpOp1P2V2': floatReg('((((op1+2)) * 4) + 2)'),
334 'AA64FpOp1P3V2': floatReg('((((op1+2)) * 4) + 3)'),
335
336 'AA64FpOp1P0V3': floatReg('((((op1+3)) * 4) + 0)'),
337 'AA64FpOp1P1V3': floatReg('((((op1+3)) * 4) + 1)'),
338 'AA64FpOp1P2V3': floatReg('((((op1+3)) * 4) + 2)'),
339 'AA64FpOp1P3V3': floatReg('((((op1+3)) * 4) + 3)'),
340
341 'AA64FpOp1P0V0S': floatReg('((((op1+0)%32) * 4) + 0)'),
342 'AA64FpOp1P1V0S': floatReg('((((op1+0)%32) * 4) + 1)'),
343 'AA64FpOp1P2V0S': floatReg('((((op1+0)%32) * 4) + 2)'),
344 'AA64FpOp1P3V0S': floatReg('((((op1+0)%32) * 4) + 3)'),
345
346 'AA64FpOp1P0V1S': floatReg('((((op1+1)%32) * 4) + 0)'),
347 'AA64FpOp1P1V1S': floatReg('((((op1+1)%32) * 4) + 1)'),
348 'AA64FpOp1P2V1S': floatReg('((((op1+1)%32) * 4) + 2)'),
349 'AA64FpOp1P3V1S': floatReg('((((op1+1)%32) * 4) + 3)'),
350
351 'AA64FpOp1P0V2S': floatReg('((((op1+2)%32) * 4) + 0)'),
352 'AA64FpOp1P1V2S': floatReg('((((op1+2)%32) * 4) + 1)'),
353 'AA64FpOp1P2V2S': floatReg('((((op1+2)%32) * 4) + 2)'),
354 'AA64FpOp1P3V2S': floatReg('((((op1+2)%32) * 4) + 3)'),
355
356 'AA64FpOp1P0V3S': floatReg('((((op1+3)%32) * 4) + 0)'),
357 'AA64FpOp1P1V3S': floatReg('((((op1+3)%32) * 4) + 1)'),
358 'AA64FpOp1P2V3S': floatReg('((((op1+3)%32) * 4) + 2)'),
359 'AA64FpOp1P3V3S': floatReg('((((op1+3)%32) * 4) + 3)'),
360
361 'AA64FpDestP0V0': floatReg('((((dest+0)) * 4) + 0)'),
362 'AA64FpDestP1V0': floatReg('((((dest+0)) * 4) + 1)'),
363 'AA64FpDestP2V0': floatReg('((((dest+0)) * 4) + 2)'),
364 'AA64FpDestP3V0': floatReg('((((dest+0)) * 4) + 3)'),
365
366 'AA64FpDestP0V1': floatReg('((((dest+1)) * 4) + 0)'),
367 'AA64FpDestP1V1': floatReg('((((dest+1)) * 4) + 1)'),
368 'AA64FpDestP2V1': floatReg('((((dest+1)) * 4) + 2)'),
369 'AA64FpDestP3V1': floatReg('((((dest+1)) * 4) + 3)'),
370
371 'AA64FpDestP0V0L': floatReg('((((dest+0)%32) * 4) + 0)'),
372 'AA64FpDestP1V0L': floatReg('((((dest+0)%32) * 4) + 1)'),
373 'AA64FpDestP2V0L': floatReg('((((dest+0)%32) * 4) + 2)'),
374 'AA64FpDestP3V0L': floatReg('((((dest+0)%32) * 4) + 3)'),
375
376 'AA64FpDestP0V1L': floatReg('((((dest+1)%32) * 4) + 0)'),
377 'AA64FpDestP1V1L': floatReg('((((dest+1)%32) * 4) + 1)'),
378 'AA64FpDestP2V1L': floatReg('((((dest+1)%32) * 4) + 2)'),
379 'AA64FpDestP3V1L': floatReg('((((dest+1)%32) * 4) + 3)'),
380
381 #Abstracted control reg operands
382 'MiscDest': cntrlReg('dest'),
383 'MiscOp1': cntrlReg('op1'),
384 'MiscNsBankedDest': cntrlNsBankedReg('dest'),
385 'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
386 'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
387 'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
388

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