sve_mem.isa (14106:293e3f4b1321) sve_mem.isa (14108:881e7d85baf7)
1// Copyright (c) 2017-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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1470 substDict = {'targs': type,
1471 'class_name': 'SveLoadRegImmMicroop' if offsetIsImm
1472 else 'SveLoadRegRegMicroop'}
1473 exec_output += SveStructMemExecDeclare.subst(substDict)
1474 substDict['class_name'] = ('SveStoreRegImmMicroop' if offsetIsImm
1475 else 'SveStoreRegRegMicroop')
1476 exec_output += SveStructMemExecDeclare.subst(substDict)
1477
1// Copyright (c) 2017-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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1470 substDict = {'targs': type,
1471 'class_name': 'SveLoadRegImmMicroop' if offsetIsImm
1472 else 'SveLoadRegRegMicroop'}
1473 exec_output += SveStructMemExecDeclare.subst(substDict)
1474 substDict['class_name'] = ('SveStoreRegImmMicroop' if offsetIsImm
1475 else 'SveStoreRegRegMicroop')
1476 exec_output += SveStructMemExecDeclare.subst(substDict)
1477
1478 # Generates definitions for SVE load-and-replicate quadword instructions
1479 def emitSveLoadAndReplQuad(offsetIsImm):
1480 global header_output, exec_output, decoders
1481 tplHeader = 'template <class RegElemType, class MemElemType>'
1482 tplArgs = '<RegElemType, MemElemType>'
1483 eaCode = SPAlignmentCheckCode + '''
1484 int memAccessSize = 16;
1485 EA = XBase + '''
1486 if offsetIsImm:
1487 eaCode += '(((int64_t) this->imm) * 16);'
1488 else:
1489 eaCode += '(XOffset * sizeof(MemElemType));'
1490 loadRdEnableCode = '''
1491 eCount = 16/sizeof(RegElemType);
1492 auto rdEn = std::vector<bool>(16, true);
1493 for (int i = 0; i < eCount; ++i) {
1494 if (!GpOp_x[i]) {
1495 for (int j = 0; j < sizeof(RegElemType); ++j) {
1496 rdEn[sizeof(RegElemType) * i + j] = false;
1497 }
1498 }
1499 }
1500 '''
1501 memAccCode = '''
1502 __uint128_t qword;
1503 RegElemType* qp = reinterpret_cast<RegElemType*>(&qword);
1504 for (int i = 0; i < 16/sizeof(RegElemType); ++i) {
1505 if (GpOp_x[i]) {
1506 qp[i] = memDataView[i];
1507 } else {
1508 qp[i] = 0;
1509 }
1510 }
1511 eCount = ArmStaticInst::getCurSveVecLen<__uint128_t>(
1512 xc->tcBase());
1513 for (int i = 0; i < eCount; ++i) {
1514 AA64FpDest_uq[i] = qword;
1515 }
1516 '''
1517 iop = InstObjParams('ld1rq',
1518 'SveLd1RqSI' if offsetIsImm else 'SveLd1RqSS',
1519 'SveContigMemSI' if offsetIsImm else 'SveContigMemSS',
1520 {'tpl_header': tplHeader,
1521 'tpl_args': tplArgs,
1522 'rden_code': loadRdEnableCode,
1523 'memacc_code': memAccCode,
1524 'ea_code': sveEnabledCheckCode + eaCode,
1525 'fault_code': '',
1526 'fa_code': ''},
1527 ['IsMemRef', 'IsLoad'])
1528 if offsetIsImm:
1529 header_output += SveContigMemSIOpDeclare.subst(iop)
1530 else:
1531 header_output += SveContigMemSSOpDeclare.subst(iop)
1532 exec_output += (
1533 SveContigLoadExecute.subst(iop) +
1534 SveContigLoadInitiateAcc.subst(iop) +
1535 SveContigLoadCompleteAcc.subst(iop))
1536 for ttype in ('uint8_t', 'uint16_t', 'uint32_t', 'uint64_t'):
1537 substDict = {'tpl_args': '<%s, %s>' % (ttype, ttype),
1538 'class_name': 'SveLd1RqSI' if offsetIsImm
1539 else 'SveLd1RqSS'}
1540 exec_output += SveContigMemExecDeclare.subst(substDict)
1541
1478 # LD1[S]{B,H,W,D} (scalar plus immediate)
1479 # ST1[S]{B,H,W,D} (scalar plus immediate)
1480 # LDNF1[S]{B,H,W,D} (scalar plus immediate)
1481 emitSveContigMemInsts(True)
1482 # LD1[S]{B,H,W,D} (scalar plus scalar)
1483 # ST1[S]{B,H,W,D} (scalar plus scalar)
1484 # LDFF1[S]{B,H,W,D} (scalar plus vector)
1485 emitSveContigMemInsts(False)
1486
1487 # LD1R[S]{B,H,W,D}
1488 emitSveLoadAndRepl()
1489
1542 # LD1[S]{B,H,W,D} (scalar plus immediate)
1543 # ST1[S]{B,H,W,D} (scalar plus immediate)
1544 # LDNF1[S]{B,H,W,D} (scalar plus immediate)
1545 emitSveContigMemInsts(True)
1546 # LD1[S]{B,H,W,D} (scalar plus scalar)
1547 # ST1[S]{B,H,W,D} (scalar plus scalar)
1548 # LDFF1[S]{B,H,W,D} (scalar plus vector)
1549 emitSveContigMemInsts(False)
1550
1551 # LD1R[S]{B,H,W,D}
1552 emitSveLoadAndRepl()
1553
1554 # LD1RQ{B,H,W,D} (scalar plus immediate)
1555 emitSveLoadAndReplQuad(offsetIsImm = True)
1556 # LD1RQ{B,H,W,D} (scalar plus scalar)
1557 emitSveLoadAndReplQuad(offsetIsImm = False)
1558
1490 # LD{2,3,4}{B,H,W,D} (scalar plus immediate)
1491 # ST{2,3,4}{B,H,W,D} (scalar plus immediate)
1492 emitSveStructMemInsts(offsetIsImm = True)
1493 # LD{2,3,4}{B,H,W,D} (scalar plus scalar)
1494 # ST{2,3,4}{B,H,W,D} (scalar plus scalar)
1495 emitSveStructMemInsts(offsetIsImm = False)
1496
1497 # LDR (predicate), STR (predicate)

--- 23 unchanged lines hidden --- 		1559 # LD{2,3,4}{B,H,W,D} (scalar plus immediate)
1560 # ST{2,3,4}{B,H,W,D} (scalar plus immediate)
1561 emitSveStructMemInsts(offsetIsImm = True)
1562 # LD{2,3,4}{B,H,W,D} (scalar plus scalar)
1563 # ST{2,3,4}{B,H,W,D} (scalar plus scalar)
1564 emitSveStructMemInsts(offsetIsImm = False)
1565
1566 # LDR (predicate), STR (predicate)

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