1// Copyright (c) 2017-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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1470 substDict = {'targs': type,
1471 'class_name': 'SveLoadRegImmMicroop' if offsetIsImm
1472 else 'SveLoadRegRegMicroop'}
1473 exec_output += SveStructMemExecDeclare.subst(substDict)
1474 substDict['class_name'] = ('SveStoreRegImmMicroop' if offsetIsImm
1475 else 'SveStoreRegRegMicroop')
1476 exec_output += SveStructMemExecDeclare.subst(substDict)
1477
1478 # LD1[S]{B,H,W,D} (scalar plus immediate)
1479 # ST1[S]{B,H,W,D} (scalar plus immediate)
1480 # LDNF1[S]{B,H,W,D} (scalar plus immediate)
1481 emitSveContigMemInsts(True)
1482 # LD1[S]{B,H,W,D} (scalar plus scalar)
1483 # ST1[S]{B,H,W,D} (scalar plus scalar)
1484 # LDFF1[S]{B,H,W,D} (scalar plus vector)
1485 emitSveContigMemInsts(False)
1486
1487 # LD1R[S]{B,H,W,D}
1488 emitSveLoadAndRepl()
1489
1490 # LD{2,3,4}{B,H,W,D} (scalar plus immediate)
1491 # ST{2,3,4}{B,H,W,D} (scalar plus immediate)
1492 emitSveStructMemInsts(offsetIsImm = True)
1493 # LD{2,3,4}{B,H,W,D} (scalar plus scalar)
1494 # ST{2,3,4}{B,H,W,D} (scalar plus scalar)
1495 emitSveStructMemInsts(offsetIsImm = False)
1496
1497 # LDR (predicate), STR (predicate)

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