sve.isa (13816:5a101ab471c9) sve.isa (13824:54e92033cf67)
1// Copyright (c) 2017-2019 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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4273 sveSpliceInst('splice', 'Splice', 'SimdAluOp', unsignedTypes)
4274 # SQADD (immediate)
4275 sqaddCode = '''
4276 destElem = srcElem1 + srcElem2;
4277 bool negDest = (destElem < 0);
4278 bool negSrc1 = (srcElem1 < 0);
4279 bool negSrc2 = (srcElem2 < 0);
4280 if ((negDest != negSrc1) && (negSrc1 == negSrc2)) {
1// Copyright (c) 2017-2019 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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4273 sveSpliceInst('splice', 'Splice', 'SimdAluOp', unsignedTypes)
4274 # SQADD (immediate)
4275 sqaddCode = '''
4276 destElem = srcElem1 + srcElem2;
4277 bool negDest = (destElem < 0);
4278 bool negSrc1 = (srcElem1 < 0);
4279 bool negSrc2 = (srcElem2 < 0);
4280 if ((negDest != negSrc1) && (negSrc1 == negSrc2)) {
4281 destElem = (Element)1 << (sizeof(Element) * 8 - 1);
4281 destElem = static_cast<Element>(
4282 (Element)1 << (sizeof(Element) * 8 - 1)
4283 );
4282 if (negDest)
4283 destElem -= 1;
4284 }
4285 '''
4286 sveWideImmInst('sqadd', 'SqaddImm', 'SimdAddOp', signedTypes, sqaddCode)
4287 # SQADD (vectors)
4288 sveBinInst('sqadd', 'Sqadd', 'SimdAddOp', signedTypes, sqaddCode)
4289 # SQDECB, SQDECH, SQDECW, SQDECD (scalar, 32-bit)
4290 sqdecCode = '''
4291 destElem = srcElem1 - (count * imm);
4292 bool negDest = (destElem < 0);
4293 bool negSrc = (srcElem1 < 0);
4294 bool posCount = ((count * imm) >= 0);
4295 if ((negDest != negSrc) && (negSrc == posCount)) {
4284 if (negDest)
4285 destElem -= 1;
4286 }
4287 '''
4288 sveWideImmInst('sqadd', 'SqaddImm', 'SimdAddOp', signedTypes, sqaddCode)
4289 # SQADD (vectors)
4290 sveBinInst('sqadd', 'Sqadd', 'SimdAddOp', signedTypes, sqaddCode)
4291 # SQDECB, SQDECH, SQDECW, SQDECD (scalar, 32-bit)
4292 sqdecCode = '''
4293 destElem = srcElem1 - (count * imm);
4294 bool negDest = (destElem < 0);
4295 bool negSrc = (srcElem1 < 0);
4296 bool posCount = ((count * imm) >= 0);
4297 if ((negDest != negSrc) && (negSrc == posCount)) {
4296 destElem = (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1);
4298 destElem = static_cast<%(dstType)s>(
4299 (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1)
4300 );
4297 if (negDest)
4298 destElem -= 1;
4299 }
4300 '''
4301 sveElemCountInst('sqdec', 'Sqdec32', 'SimdAluOp', signedTypes,
4302 sqdecCode%{'dstType':'int32_t'}, destType = DestType.Scalar,
4303 dstIs32b = True)
4304 # SQDECB, SQDECH, SQDECW, SQDECD (scalar, 64-bit)

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4345 sqdecpCode % 'Element', DestType.Vector)
4346 # SQINCB, SQINCH, SQINCW, SQINCD (scalar, 32-bit)
4347 sqincCode = '''
4348 destElem = srcElem1 + (count * imm);
4349 bool negDest = (destElem < 0);
4350 bool negSrc = (srcElem1 < 0);
4351 bool negCount = ((count * imm) < 0);
4352 if ((negDest != negSrc) && (negSrc == negCount)) {
4301 if (negDest)
4302 destElem -= 1;
4303 }
4304 '''
4305 sveElemCountInst('sqdec', 'Sqdec32', 'SimdAluOp', signedTypes,
4306 sqdecCode%{'dstType':'int32_t'}, destType = DestType.Scalar,
4307 dstIs32b = True)
4308 # SQDECB, SQDECH, SQDECW, SQDECD (scalar, 64-bit)

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4349 sqdecpCode % 'Element', DestType.Vector)
4350 # SQINCB, SQINCH, SQINCW, SQINCD (scalar, 32-bit)
4351 sqincCode = '''
4352 destElem = srcElem1 + (count * imm);
4353 bool negDest = (destElem < 0);
4354 bool negSrc = (srcElem1 < 0);
4355 bool negCount = ((count * imm) < 0);
4356 if ((negDest != negSrc) && (negSrc == negCount)) {
4353 destElem = (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1);
4357 destElem = static_cast<%(dstType)s>(
4358 (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1)
4359 );
4354 if (negDest)
4355 destElem -= 1;
4356 }
4357 '''
4358 sveElemCountInst('sqinc', 'Sqinc32', 'SimdAluOp', signedTypes,
4359 sqincCode%{'dstType':'int32_t'}, destType = DestType.Scalar,
4360 dstIs32b = True)
4361 # SQINCB, SQINCH, SQINCW, SQINCD (scalar, 64-bit)

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4402 sqincpCode % 'Element', DestType.Vector)
4403 # SQSUB (immediate)
4404 sqsubCode = '''
4405 destElem = srcElem1 - srcElem2;
4406 bool negDest = (destElem < 0);
4407 bool negSrc1 = (srcElem1 < 0);
4408 bool posSrc2 = (srcElem2 >= 0);
4409 if ((negDest != negSrc1) && (negSrc1 == posSrc2)) {
4360 if (negDest)
4361 destElem -= 1;
4362 }
4363 '''
4364 sveElemCountInst('sqinc', 'Sqinc32', 'SimdAluOp', signedTypes,
4365 sqincCode%{'dstType':'int32_t'}, destType = DestType.Scalar,
4366 dstIs32b = True)
4367 # SQINCB, SQINCH, SQINCW, SQINCD (scalar, 64-bit)

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4408 sqincpCode % 'Element', DestType.Vector)
4409 # SQSUB (immediate)
4410 sqsubCode = '''
4411 destElem = srcElem1 - srcElem2;
4412 bool negDest = (destElem < 0);
4413 bool negSrc1 = (srcElem1 < 0);
4414 bool posSrc2 = (srcElem2 >= 0);
4415 if ((negDest != negSrc1) && (negSrc1 == posSrc2)) {
4410 destElem = (Element)1 << (sizeof(Element) * 8 - 1);
4416 destElem = static_cast<Element>(
4417 (Element)1 << (sizeof(Element) * 8 - 1)
4418 );
4411 if (negDest)
4412 destElem -= 1;
4413 }
4414 '''
4415 sveWideImmInst('sqsub', 'SqsubImm', 'SimdAddOp', signedTypes, sqsubCode)
4416 # SQSUB (vectors)
4417 sveBinInst('sqsub', 'Sqsub', 'SimdAddOp', signedTypes, sqsubCode)
4418 # SUB (immediate)

--- 380 unchanged lines hidden --- 		4419 if (negDest)
4420 destElem -= 1;
4421 }
4422 '''
4423 sveWideImmInst('sqsub', 'SqsubImm', 'SimdAddOp', signedTypes, sqsubCode)
4424 # SQSUB (vectors)
4425 sveBinInst('sqsub', 'Sqsub', 'SimdAddOp', signedTypes, sqsubCode)
4426 # SUB (immediate)

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