1// -*- mode: c++ -*- 2 3// Copyright (c) 2012-2014 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 171 unchanged lines hidden (view full) --- 180 getInputCodeOp1S += ''' 181 writeVecElem(&input[%(v)d], (XReg) AA64FpOp1P%(p)dV%(v)dS_uw, 182 %(p)d, 0x2); 183 ''' % { 'v' : v, 'p' : p } 184 185 if name == 'deint_neon_uop': 186 187 eCode = ''' |
188 // input data from scratch area 189 VReg input[4] = { {0, 0}, {0, 0}, {0, 0}, {0, 0} }; |
190 VReg output[2]; // output data to arch. SIMD regs 191 VReg temp; 192 temp.lo = 0; 193 temp.hi = 0; 194 ''' 195 for p in range(4): 196 eCode += ''' 197 writeVecElem(&temp, (XReg) AA64FpDestP%(p)dV1L_uw, %(p)d, 0x2); --- 68 unchanged lines hidden (view full) --- 266 { 'code' : eCode, 'op_class' : 'No_OpClass' }, 267 ['IsMicroop']) 268 header_output += MicroNeonMixDeclare64.subst(iop) 269 exec_output += MicroNeonMixExecute64.subst(iop) 270 271 elif name == 'int_neon_uop': 272 273 eCode = ''' |
274 // input data from arch. SIMD regs 275 VReg input[4] = { {0, 0}, {0, 0}, {0, 0}, {0, 0} }; |
276 VReg output[2]; // output data to scratch area 277 ''' 278 279 eCode += getInputCodeOp1S 280 281 # Note that numRegs is not always the same as numStructElems; in 282 # particular, for LD1/ST1, numStructElems is 1 but numRegs can be 283 # 1, 2, 3 or 4 --- 45 unchanged lines hidden (view full) --- 329 { 'code' : eCode, 'op_class' : 'No_OpClass' }, 330 ['IsMicroop']) 331 header_output += MicroNeonMixDeclare64.subst(iop) 332 exec_output += MicroNeonMixExecute64.subst(iop) 333 334 elif name == 'unpack_neon_uop': 335 336 eCode = ''' |
337 //input data from scratch area 338 VReg input[4] = { {0, 0}, {0, 0}, {0, 0}, {0, 0} }; |
339 VReg output[2]; //output data to arch. SIMD regs 340 ''' 341 342 eCode += getInputCodeOp1L 343 344 # Fill output regs with register data initially. Note that 345 # elements in output register outside indexed lanes are left 346 # untouched --- 49 unchanged lines hidden (view full) --- 396 iop = InstObjParams(name, Name, 'MicroNeonMixLaneOp64', 397 { 'code' : eCode }, ['IsMicroop']) 398 header_output += MicroNeonMixLaneDeclare64.subst(iop) 399 exec_output += MicroNeonMixExecute64.subst(iop) 400 401 elif name == 'pack_neon_uop': 402 403 eCode = ''' |
404 // input data from arch. SIMD regs 405 VReg input[4] = { {0, 0}, {0, 0}, {0, 0}, {0, 0} }; |
406 VReg output[2]; // output data to scratch area 407 ''' 408 409 eCode += getInputCodeOp1S 410 411 eCode += ''' 412 int eSizeBytes = 1 << eSize; 413 int numOutputElems = 128 / (8 << eSize); --- 70 unchanged lines hidden --- |