neon64.isa (13120:690a0db8e58b) neon64.isa (13544:0b4e5446167c)
1// -*- mode: c++ -*-
2
3// Copyright (c) 2012-2013, 2015-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 814 unchanged lines hidden (view full) ---

823 exec_output += NeonXExecDeclare.subst(substDict)
824
825 def tbxTblInstX(name, Name, opClass, types, length, isTbl, rCount):
826 global header_output, decoder_output, exec_output
827 code = simd64EnabledCheckCode + '''
828 union
829 {
830 uint8_t bytes[64];
1// -*- mode: c++ -*-
2
3// Copyright (c) 2012-2013, 2015-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 814 unchanged lines hidden (view full) ---

823 exec_output += NeonXExecDeclare.subst(substDict)
824
825 def tbxTblInstX(name, Name, opClass, types, length, isTbl, rCount):
826 global header_output, decoder_output, exec_output
827 code = simd64EnabledCheckCode + '''
828 union
829 {
830 uint8_t bytes[64];
831 FloatRegBits regs[16];
831 uint32_t regs[16];
832 } table;
833
834 union
835 {
836 uint8_t bytes[%(rCount)d * 4];
832 } table;
833
834 union
835 {
836 uint8_t bytes[%(rCount)d * 4];
837 FloatRegBits regs[%(rCount)d];
837 uint32_t regs[%(rCount)d];
838 } destReg, srcReg2;
839
840 const unsigned length = %(length)d;
841 const bool isTbl = %(isTbl)s;
842 ''' % { "rCount" : rCount, "length" : length, "isTbl" : isTbl }
843 for reg in range(rCount):
844 code += '''
845 srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);

--- 2537 unchanged lines hidden --- 		838 } destReg, srcReg2;
839
840 const unsigned length = %(length)d;
841 const bool isTbl = %(isTbl)s;
842 ''' % { "rCount" : rCount, "length" : length, "isTbl" : isTbl }
843 for reg in range(rCount):
844 code += '''
845 srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);

--- 2537 unchanged lines hidden ---