neon64.isa (12110:c24ee249b8ba) neon64.isa (13120:690a0db8e58b)
1// -*- mode: c++ -*-
2
1// -*- mode: c++ -*-
2
3// Copyright (c) 2012-2013, 2015-2016 ARM Limited
3// Copyright (c) 2012-2013, 2015-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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40
41let {{
42
43 header_output = ""
44 exec_output = ""
45 decoders = { 'Generic' : {} }
46
47 # FP types (FP operations always work with unsigned representations)
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 28 unchanged lines hidden (view full) ---

40
41let {{
42
43 header_output = ""
44 exec_output = ""
45 decoders = { 'Generic' : {} }
46
47 # FP types (FP operations always work with unsigned representations)
48 floatTypes = ("uint32_t", "uint64_t")
48 floatTypes = ("uint16_t", "uint32_t", "uint64_t")
49 smallFloatTypes = ("uint32_t",)
50
51 def threeEqualRegInstX(name, Name, opClass, types, rCount, op,
52 readDest=False, pairwise=False, scalar=False,
53 byElem=False, decoder='Generic'):
54 assert (not pairwise) or ((not byElem) and (not scalar))
55 global header_output, exec_output, decoders
56 eWalkCode = simd64EnabledCheckCode + '''

--- 3326 unchanged lines hidden --- 		49 smallFloatTypes = ("uint32_t",)
50
51 def threeEqualRegInstX(name, Name, opClass, types, rCount, op,
52 readDest=False, pairwise=False, scalar=False,
53 byElem=False, decoder='Generic'):
54 assert (not pairwise) or ((not byElem) and (not scalar))
55 global header_output, exec_output, decoders
56 eWalkCode = simd64EnabledCheckCode + '''

--- 3326 unchanged lines hidden ---