1// -*- mode: c++ -*- 2 |
3// Copyright (c) 2012-2013, 2015 ARM Limited |
4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 25 unchanged lines hidden (view full) --- 37// 38// Authors: Giacomo Gabrielli 39// Mbou Eyole 40 41let {{ 42 43 header_output = "" 44 exec_output = "" |
45 decoders = { 'Generic' : {} } |
46 47 # FP types (FP operations always work with unsigned representations) 48 floatTypes = ("uint32_t", "uint64_t") 49 smallFloatTypes = ("uint32_t",) 50 51 def threeEqualRegInstX(name, Name, opClass, types, rCount, op, 52 readDest=False, pairwise=False, scalar=False, |
53 byElem=False, decoder='Generic'): |
54 assert (not pairwise) or ((not byElem) and (not scalar)) |
55 global header_output, exec_output, decoders |
56 eWalkCode = simd64EnabledCheckCode + ''' 57 RegVect srcReg1, destReg; 58 ''' 59 if byElem: 60 # 2nd register operand has to be read fully 61 eWalkCode += ''' 62 FullRegVect srcReg2; 63 ''' --- 3288 unchanged lines hidden (view full) --- 3352 threeRegScrambleInstX("zip1", "Zip1QX", "SimdAluOp", unsignedTypes, 4, 3353 zipCode % "0") 3354 # ZIP2 3355 threeRegScrambleInstX("zip2", "Zip2DX", "SimdAluOp", smallUnsignedTypes, 2, 3356 zipCode % "eCount / 2") 3357 threeRegScrambleInstX("zip2", "Zip2QX", "SimdAluOp", unsignedTypes, 4, 3358 zipCode % "eCount / 2") 3359 |
3360 for decoderFlavour, type_dict in decoders.iteritems(): 3361 header_output += ''' 3362 class %(decoder_flavour)sDecoder { 3363 public: 3364 ''' % { "decoder_flavour" : decoderFlavour } 3365 for type,name in type_dict.iteritems(): 3366 header_output += ''' 3367 template<typename Elem> using %(type)s = %(new_name)s<Elem>;''' % { 3368 "type" : type, "new_name" : name 3369 } 3370 header_output += ''' 3371 };''' |
3372}}; |