1// -*- mode: c++ -*-
2
3// Copyright (c) 2012-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 25 unchanged lines hidden (view full) ---

37//
38// Authors: Giacomo Gabrielli
39// Mbou Eyole
40
41let {{
42
43 header_output = ""
44 exec_output = ""
45
46 # FP types (FP operations always work with unsigned representations)
47 floatTypes = ("uint32_t", "uint64_t")
48 smallFloatTypes = ("uint32_t",)
49
50 def threeEqualRegInstX(name, Name, opClass, types, rCount, op,
51 readDest=False, pairwise=False, scalar=False,
52 byElem=False):
53 assert (not pairwise) or ((not byElem) and (not scalar))
54 global header_output, exec_output
55 eWalkCode = simd64EnabledCheckCode + '''
56 RegVect srcReg1, destReg;
57 '''
58 if byElem:
59 # 2nd register operand has to be read fully
60 eWalkCode += '''
61 FullRegVect srcReg2;
62 '''

--- 3288 unchanged lines hidden (view full) ---

3351 threeRegScrambleInstX("zip1", "Zip1QX", "SimdAluOp", unsignedTypes, 4,
3352 zipCode % "0")
3353 # ZIP2
3354 threeRegScrambleInstX("zip2", "Zip2DX", "SimdAluOp", smallUnsignedTypes, 2,
3355 zipCode % "eCount / 2")
3356 threeRegScrambleInstX("zip2", "Zip2QX", "SimdAluOp", unsignedTypes, 4,
3357 zipCode % "eCount / 2")
3358
3359}};