neon.isa (8607:5fb918115c07) neon.isa (8782:10c9297e14d5)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 858 unchanged lines hidden (view full) ---

867 eWalkCode += '''
868 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
869 ''' % { "reg" : reg }
870 readDestCode = ''
871 if readDest:
872 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
873 eWalkCode += '''
874 if (imm < 0 && imm >= eCount) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 858 unchanged lines hidden (view full) ---

867 eWalkCode += '''
868 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
869 ''' % { "reg" : reg }
870 readDestCode = ''
871 if readDest:
872 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
873 eWalkCode += '''
874 if (imm < 0 && imm >= eCount) {
875#if FULL_SYSTEM
876 fault = new UndefinedInstruction;
877#else
878 fault = new UndefinedInstruction(false, mnemonic);
879#endif
875 if (FullSystem)
876 fault = new UndefinedInstruction;
877 else
878 fault = new UndefinedInstruction(false, mnemonic);
880 } else {
881 for (unsigned i = 0; i < eCount; i++) {
882 Element srcElem1 = gtoh(srcReg1.elements[i]);
883 Element srcElem2 = gtoh(srcReg2.elements[imm]);
884 Element destElem;
885 %(readDest)s
886 %(op)s
887 destReg.elements[i] = htog(destElem);

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922 eWalkCode += '''
923 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
924 ''' % { "reg" : reg }
925 readDestCode = ''
926 if readDest:
927 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
928 eWalkCode += '''
929 if (imm < 0 && imm >= eCount) {
879 } else {
880 for (unsigned i = 0; i < eCount; i++) {
881 Element srcElem1 = gtoh(srcReg1.elements[i]);
882 Element srcElem2 = gtoh(srcReg2.elements[imm]);
883 Element destElem;
884 %(readDest)s
885 %(op)s
886 destReg.elements[i] = htog(destElem);

--- 34 unchanged lines hidden (view full) ---

921 eWalkCode += '''
922 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
923 ''' % { "reg" : reg }
924 readDestCode = ''
925 if readDest:
926 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
927 eWalkCode += '''
928 if (imm < 0 && imm >= eCount) {
930#if FULL_SYSTEM
931 fault = new UndefinedInstruction;
932#else
933 fault = new UndefinedInstruction(false, mnemonic);
934#endif
929 if (FullSystem)
930 fault = new UndefinedInstruction;
931 else
932 fault = new UndefinedInstruction(false, mnemonic);
935 } else {
936 for (unsigned i = 0; i < eCount; i++) {
937 Element srcElem1 = gtoh(srcReg1.elements[i]);
938 Element srcElem2 = gtoh(srcReg2.elements[imm]);
939 BigElement destElem;
940 %(readDest)s
941 %(op)s
942 destReg.elements[i] = htog(destElem);

--- 32 unchanged lines hidden (view full) ---

975 eWalkCode += '''
976 destRegs[%(reg)d] = FpDestP%(reg)d;
977 ''' % { "reg" : reg }
978 readDestCode = ''
979 if readDest:
980 readDestCode = 'destReg = destRegs[i];'
981 eWalkCode += '''
982 if (imm < 0 && imm >= eCount) {
933 } else {
934 for (unsigned i = 0; i < eCount; i++) {
935 Element srcElem1 = gtoh(srcReg1.elements[i]);
936 Element srcElem2 = gtoh(srcReg2.elements[imm]);
937 BigElement destElem;
938 %(readDest)s
939 %(op)s
940 destReg.elements[i] = htog(destElem);

--- 32 unchanged lines hidden (view full) ---

973 eWalkCode += '''
974 destRegs[%(reg)d] = FpDestP%(reg)d;
975 ''' % { "reg" : reg }
976 readDestCode = ''
977 if readDest:
978 readDestCode = 'destReg = destRegs[i];'
979 eWalkCode += '''
980 if (imm < 0 && imm >= eCount) {
983#if FULL_SYSTEM
984 fault = new UndefinedInstruction;
985#else
986 fault = new UndefinedInstruction(false, mnemonic);
987#endif
981 if (FullSystem)
982 fault = new UndefinedInstruction;
983 else
984 fault = new UndefinedInstruction(false, mnemonic);
988 } else {
989 for (unsigned i = 0; i < rCount; i++) {
990 FloatReg srcReg1 = srcRegs1[i];
991 FloatReg srcReg2 = srcRegs2[imm];
992 FloatReg destReg;
993 %(readDest)s
994 %(op)s
995 destRegs[i] = destReg;

--- 618 unchanged lines hidden (view full) ---

1614 threeEqualRegInst("vmin", "VminQ", "SimdCmpOp", allTypes, 4, vminCode)
1615
1616 vaddCode = '''
1617 destElem = srcElem1 + srcElem2;
1618 '''
1619 threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode)
1620 threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode)
1621
985 } else {
986 for (unsigned i = 0; i < rCount; i++) {
987 FloatReg srcReg1 = srcRegs1[i];
988 FloatReg srcReg2 = srcRegs2[imm];
989 FloatReg destReg;
990 %(readDest)s
991 %(op)s
992 destRegs[i] = destReg;

--- 618 unchanged lines hidden (view full) ---

1611 threeEqualRegInst("vmin", "VminQ", "SimdCmpOp", allTypes, 4, vminCode)
1612
1613 vaddCode = '''
1614 destElem = srcElem1 + srcElem2;
1615 '''
1616 threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode)
1617 threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode)
1618
1622 threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes,
1619 threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes,
1623 2, vaddCode, pairwise=True)
1620 2, vaddCode, pairwise=True)
1621 threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes,
1622 4, vaddCode, pairwise=True)
1624 vaddlwCode = '''
1625 destElem = (BigElement)srcElem1 + (BigElement)srcElem2;
1626 '''
1627 threeRegLongInst("vaddl", "Vaddl", "SimdAddOp", smallTypes, vaddlwCode)
1628 threeRegWideInst("vaddw", "Vaddw", "SimdAddOp", smallTypes, vaddlwCode)
1629 vaddhnCode = '''
1630 destElem = ((BigElement)srcElem1 + (BigElement)srcElem2) >>
1631 (sizeof(Element) * 8);

--- 474 unchanged lines hidden (view full) ---

2106 destElem = 0;
2107 for (unsigned j = 0; j < sizeof(Element) * 8; j++) {
2108 if (bits(srcElem2, j))
2109 destElem ^= (BigElement)srcElem1 << j;
2110 }
2111 '''
2112 threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode)
2113
1623 vaddlwCode = '''
1624 destElem = (BigElement)srcElem1 + (BigElement)srcElem2;
1625 '''
1626 threeRegLongInst("vaddl", "Vaddl", "SimdAddOp", smallTypes, vaddlwCode)
1627 threeRegWideInst("vaddw", "Vaddw", "SimdAddOp", smallTypes, vaddlwCode)
1628 vaddhnCode = '''
1629 destElem = ((BigElement)srcElem1 + (BigElement)srcElem2) >>
1630 (sizeof(Element) * 8);

--- 474 unchanged lines hidden (view full) ---

2105 destElem = 0;
2106 for (unsigned j = 0; j < sizeof(Element) * 8; j++) {
2107 if (bits(srcElem2, j))
2108 destElem ^= (BigElement)srcElem1 << j;
2109 }
2110 '''
2111 threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode)
2112
2114 threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True)
2113 threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True)
2114 threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True)
2115
2115
2116 threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True)
2116 threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True)
2117 threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True)
2117
2118 vqdmulhCode = '''
2119 FPSCR fpscr = (FPSCR) FpscrQc;
2120 destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2) >>
2121 (sizeof(Element) * 8);
2122 if (srcElem1 == srcElem2 &&
2123 srcElem1 == (Element)((Element)1 <<
2124 (sizeof(Element) * 8 - 1))) {

--- 1006 unchanged lines hidden (view full) ---

3131 vtrnCode = '''
3132 Element mid;
3133 for (unsigned i = 0; i < eCount; i += 2) {
3134 mid = srcReg1.elements[i];
3135 srcReg1.elements[i] = destReg.elements[i + 1];
3136 destReg.elements[i + 1] = mid;
3137 }
3138 '''
2118
2119 vqdmulhCode = '''
2120 FPSCR fpscr = (FPSCR) FpscrQc;
2121 destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2) >>
2122 (sizeof(Element) * 8);
2123 if (srcElem1 == srcElem2 &&
2124 srcElem1 == (Element)((Element)1 <<
2125 (sizeof(Element) * 8 - 1))) {

--- 1006 unchanged lines hidden (view full) ---

3132 vtrnCode = '''
3133 Element mid;
3134 for (unsigned i = 0; i < eCount; i += 2) {
3135 mid = srcReg1.elements[i];
3136 srcReg1.elements[i] = destReg.elements[i + 1];
3137 destReg.elements[i + 1] = mid;
3138 }
3139 '''
3139 twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp",
3140 smallUnsignedTypes, 2, vtrnCode)
3141 twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp",
3142 smallUnsignedTypes, 4, vtrnCode)
3140 twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode)
3141 twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode)
3143
3144 vuzpCode = '''
3145 Element mid[eCount];
3146 memcpy(&mid, &srcReg1, sizeof(srcReg1));
3147 for (unsigned i = 0; i < eCount / 2; i++) {
3148 srcReg1.elements[i] = destReg.elements[2 * i + 1];
3149 srcReg1.elements[eCount / 2 + i] = mid[2 * i + 1];
3150 destReg.elements[i] = destReg.elements[2 * i];

--- 140 unchanged lines hidden (view full) ---

3291
3292 vextCode = '''
3293 for (unsigned i = 0; i < eCount; i++) {
3294 unsigned index = i + imm;
3295 if (index < eCount) {
3296 destReg.elements[i] = srcReg1.elements[index];
3297 } else {
3298 index -= eCount;
3142
3143 vuzpCode = '''
3144 Element mid[eCount];
3145 memcpy(&mid, &srcReg1, sizeof(srcReg1));
3146 for (unsigned i = 0; i < eCount / 2; i++) {
3147 srcReg1.elements[i] = destReg.elements[2 * i + 1];
3148 srcReg1.elements[eCount / 2 + i] = mid[2 * i + 1];
3149 destReg.elements[i] = destReg.elements[2 * i];

--- 140 unchanged lines hidden (view full) ---

3290
3291 vextCode = '''
3292 for (unsigned i = 0; i < eCount; i++) {
3293 unsigned index = i + imm;
3294 if (index < eCount) {
3295 destReg.elements[i] = srcReg1.elements[index];
3296 } else {
3297 index -= eCount;
3299 if (index >= eCount)
3300#if FULL_SYSTEM
3301 fault = new UndefinedInstruction;
3302#else
3303 fault = new UndefinedInstruction(false, mnemonic);
3304#endif
3305 else
3298 if (index >= eCount) {
3299 if (FullSystem)
3300 fault = new UndefinedInstruction;
3301 else
3302 fault = new UndefinedInstruction(false, mnemonic);
3303 } else {
3306 destReg.elements[i] = srcReg2.elements[index];
3304 destReg.elements[i] = srcReg2.elements[index];
3305 }
3307 }
3308 }
3309 '''
3310 buildVext("vext", "NVextD", "SimdMiscOp", ("uint8_t",), 2, vextCode)
3311 buildVext("vext", "NVextQ", "SimdMiscOp", ("uint8_t",), 4, vextCode)
3312
3313 def buildVtbxl(name, Name, opClass, length, isVtbl):
3314 global header_output, decoder_output, exec_output

--- 62 unchanged lines hidden --- 		3306 }
3307 }
3308 '''
3309 buildVext("vext", "NVextD", "SimdMiscOp", ("uint8_t",), 2, vextCode)
3310 buildVext("vext", "NVextQ", "SimdMiscOp", ("uint8_t",), 4, vextCode)
3311
3312 def buildVtbxl(name, Name, opClass, length, isVtbl):
3313 global header_output, decoder_output, exec_output

--- 62 unchanged lines hidden ---