Cross Reference: /gem5/src/arch/arm/isa/insts/neon.isa

1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 625 unchanged lines hidden (view full) ---

634 def threeEqualRegInst(name, Name, opClass, types, rCount, op,
635 readDest=False, pairwise=False):
636 global header_output, exec_output
637 eWalkCode = simdEnabledCheckCode + '''
638 RegVect srcReg1, srcReg2, destReg;
639 '''
640 for reg in range(rCount):
641 eWalkCode += '''

642 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
643 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);

642 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
643 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);

644 ''' % { "reg" : reg }
645 if readDest:
646 eWalkCode += '''

647 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

647 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

648 ''' % { "reg" : reg }
649 readDestCode = ''
650 if readDest:
651 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
652 if pairwise:
653 eWalkCode += '''
654 for (unsigned i = 0; i < eCount; i++) {
655 Element srcElem1 = gtoh(2 * i < eCount ?

--- 16 unchanged lines hidden (view full) ---

672 Element destElem;
673 %(readDest)s
674 %(op)s
675 destReg.elements[i] = htog(destElem);
676 }
677 ''' % { "op" : op, "readDest" : readDestCode }
678 for reg in range(rCount):
679 eWalkCode += '''

680 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

680 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

681 ''' % { "reg" : reg }
682 iop = InstObjParams(name, Name,
683 "RegRegRegOp",
684 { "code": eWalkCode,
685 "r_count": rCount,
686 "predicate_test": predicateTest,
687 "op_class": opClass }, [])
688 header_output += NeonRegRegRegOpDeclare.subst(iop)

--- 64 unchanged lines hidden (view full) ---

753 }
754 ''' % { "op" : op,
755 "readDest" : readDestCode,
756 "destType" : destType,
757 "writeDest" : writeDest }
758 for reg in range(rCount):
759 if toInt:
760 eWalkCode += '''

761 FpDestP%(reg)d.uw = destRegs.regs[%(reg)d];

761 FpDestP%(reg)d_uw = destRegs.regs[%(reg)d];

762 ''' % { "reg" : reg }
763 else:
764 eWalkCode += '''
765 FpDestP%(reg)d = destRegs[%(reg)d];
766 ''' % { "reg" : reg }
767 iop = InstObjParams(name, Name,
768 "FpRegRegRegOp",
769 { "code": eWalkCode,

--- 23 unchanged lines hidden (view full) ---

793 destPrefix = 'Big'
794 eWalkCode = simdEnabledCheckCode + '''
795 %sRegVect srcReg1;
796 %sRegVect srcReg2;
797 %sRegVect destReg;
798 ''' % (src1Prefix, src2Prefix, destPrefix)
799 for reg in range(src1Cnt):
800 eWalkCode += '''

801 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);

801 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);

802 ''' % { "reg" : reg }
803 for reg in range(src2Cnt):
804 eWalkCode += '''

805 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);

805 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);

806 ''' % { "reg" : reg }
807 if readDest:
808 for reg in range(destCnt):
809 eWalkCode += '''

810 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

810 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

811 ''' % { "reg" : reg }
812 readDestCode = ''
813 if readDest:
814 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
815 eWalkCode += '''
816 for (unsigned i = 0; i < eCount; i++) {
817 %(src1Prefix)sElement srcElem1 = gtoh(srcReg1.elements[i]);
818 %(src1Prefix)sElement srcElem2 = gtoh(srcReg2.elements[i]);
819 %(destPrefix)sElement destElem;
820 %(readDest)s
821 %(op)s
822 destReg.elements[i] = htog(destElem);
823 }
824 ''' % { "op" : op, "readDest" : readDestCode,
825 "src1Prefix" : src1Prefix, "src2Prefix" : src2Prefix,
826 "destPrefix" : destPrefix }
827 for reg in range(destCnt):
828 eWalkCode += '''

829 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

829 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

830 ''' % { "reg" : reg }
831 iop = InstObjParams(name, Name,
832 "RegRegRegOp",
833 { "code": eWalkCode,
834 "r_count": 2,
835 "predicate_test": predicateTest,
836 "op_class": opClass }, [])
837 header_output += NeonRegRegRegOpDeclare.subst(iop)

--- 17 unchanged lines hidden (view full) ---

855
856 def twoEqualRegInst(name, Name, opClass, types, rCount, op, readDest=False):
857 global header_output, exec_output
858 eWalkCode = simdEnabledCheckCode + '''
859 RegVect srcReg1, srcReg2, destReg;
860 '''
861 for reg in range(rCount):
862 eWalkCode += '''

863 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
864 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);

863 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
864 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);

865 ''' % { "reg" : reg }
866 if readDest:
867 eWalkCode += '''

868 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

868 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

869 ''' % { "reg" : reg }
870 readDestCode = ''
871 if readDest:
872 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
873 eWalkCode += '''
874 if (imm < 0 && imm >= eCount) {
875#if FULL_SYSTEM
876 fault = new UndefinedInstruction;

--- 8 unchanged lines hidden (view full) ---

885 %(readDest)s
886 %(op)s
887 destReg.elements[i] = htog(destElem);
888 }
889 }
890 ''' % { "op" : op, "readDest" : readDestCode }
891 for reg in range(rCount):
892 eWalkCode += '''

893 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

893 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

894 ''' % { "reg" : reg }
895 iop = InstObjParams(name, Name,
896 "RegRegRegImmOp",
897 { "code": eWalkCode,
898 "r_count": rCount,
899 "predicate_test": predicateTest,
900 "op_class": opClass }, [])
901 header_output += NeonRegRegRegImmOpDeclare.subst(iop)

--- 7 unchanged lines hidden (view full) ---

909 global header_output, exec_output
910 rCount = 2
911 eWalkCode = simdEnabledCheckCode + '''
912 RegVect srcReg1, srcReg2;
913 BigRegVect destReg;
914 '''
915 for reg in range(rCount):
916 eWalkCode += '''

917 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
918 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);;

917 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
918 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);;

919 ''' % { "reg" : reg }
920 if readDest:
921 for reg in range(2 * rCount):
922 eWalkCode += '''

923 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

923 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

924 ''' % { "reg" : reg }
925 readDestCode = ''
926 if readDest:
927 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
928 eWalkCode += '''
929 if (imm < 0 && imm >= eCount) {
930#if FULL_SYSTEM
931 fault = new UndefinedInstruction;

--- 8 unchanged lines hidden (view full) ---

940 %(readDest)s
941 %(op)s
942 destReg.elements[i] = htog(destElem);
943 }
944 }
945 ''' % { "op" : op, "readDest" : readDestCode }
946 for reg in range(2 * rCount):
947 eWalkCode += '''

948 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

948 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

949 ''' % { "reg" : reg }
950 iop = InstObjParams(name, Name,
951 "RegRegRegImmOp",
952 { "code": eWalkCode,
953 "r_count": rCount,
954 "predicate_test": predicateTest,
955 "op_class": opClass }, [])
956 header_output += NeonRegRegRegImmOpDeclare.subst(iop)

--- 59 unchanged lines hidden (view full) ---

1016 def twoRegShiftInst(name, Name, opClass, types, rCount, op,
1017 readDest=False, toInt=False, fromInt=False):
1018 global header_output, exec_output
1019 eWalkCode = simdEnabledCheckCode + '''
1020 RegVect srcRegs1, destRegs;
1021 '''
1022 for reg in range(rCount):
1023 eWalkCode += '''

1024 srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);

1024 srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);

1025 ''' % { "reg" : reg }
1026 if readDest:
1027 eWalkCode += '''

1028 destRegs.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1028 destRegs.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1029 ''' % { "reg" : reg }
1030 readDestCode = ''
1031 if readDest:
1032 readDestCode = 'destElem = gtoh(destRegs.elements[i]);'
1033 if toInt:
1034 readDestCode = 'destReg = gtoh(destRegs.regs[i]);'
1035 readOpCode = 'Element srcElem1 = gtoh(srcRegs1.elements[i]);'
1036 if fromInt:

--- 13 unchanged lines hidden (view full) ---

1050 }
1051 ''' % { "readOp" : readOpCode,
1052 "declDest" : declDest,
1053 "readDest" : readDestCode,
1054 "op" : op,
1055 "writeDest" : writeDestCode }
1056 for reg in range(rCount):
1057 eWalkCode += '''

1058 FpDestP%(reg)d.uw = gtoh(destRegs.regs[%(reg)d]);

1058 FpDestP%(reg)d_uw = gtoh(destRegs.regs[%(reg)d]);

1059 ''' % { "reg" : reg }
1060 iop = InstObjParams(name, Name,
1061 "RegRegImmOp",
1062 { "code": eWalkCode,
1063 "r_count": rCount,
1064 "predicate_test": predicateTest,
1065 "op_class": opClass }, [])
1066 header_output += NeonRegRegImmOpDeclare.subst(iop)

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1073 def twoRegNarrowShiftInst(name, Name, opClass, types, op, readDest=False):
1074 global header_output, exec_output
1075 eWalkCode = simdEnabledCheckCode + '''
1076 BigRegVect srcReg1;
1077 RegVect destReg;
1078 '''
1079 for reg in range(4):
1080 eWalkCode += '''

1081 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);

1081 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);

1082 ''' % { "reg" : reg }
1083 if readDest:
1084 for reg in range(2):
1085 eWalkCode += '''

1086 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1086 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1087 ''' % { "reg" : reg }
1088 readDestCode = ''
1089 if readDest:
1090 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
1091 eWalkCode += '''
1092 for (unsigned i = 0; i < eCount; i++) {
1093 BigElement srcElem1 = gtoh(srcReg1.elements[i]);
1094 Element destElem;
1095 %(readDest)s
1096 %(op)s
1097 destReg.elements[i] = htog(destElem);
1098 }
1099 ''' % { "op" : op, "readDest" : readDestCode }
1100 for reg in range(2):
1101 eWalkCode += '''

1102 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

1102 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

1103 ''' % { "reg" : reg }
1104 iop = InstObjParams(name, Name,
1105 "RegRegImmOp",
1106 { "code": eWalkCode,
1107 "r_count": 2,
1108 "predicate_test": predicateTest,
1109 "op_class": opClass }, [])
1110 header_output += NeonRegRegImmOpDeclare.subst(iop)

--- 6 unchanged lines hidden (view full) ---

1117 def twoRegLongShiftInst(name, Name, opClass, types, op, readDest=False):
1118 global header_output, exec_output
1119 eWalkCode = simdEnabledCheckCode + '''
1120 RegVect srcReg1;
1121 BigRegVect destReg;
1122 '''
1123 for reg in range(2):
1124 eWalkCode += '''

1125 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);

1125 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);

1126 ''' % { "reg" : reg }
1127 if readDest:
1128 for reg in range(4):
1129 eWalkCode += '''

1130 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1130 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1131 ''' % { "reg" : reg }
1132 readDestCode = ''
1133 if readDest:
1134 readDestCode = 'destReg = gtoh(destReg.elements[i]);'
1135 eWalkCode += '''
1136 for (unsigned i = 0; i < eCount; i++) {
1137 Element srcElem1 = gtoh(srcReg1.elements[i]);
1138 BigElement destElem;
1139 %(readDest)s
1140 %(op)s
1141 destReg.elements[i] = htog(destElem);
1142 }
1143 ''' % { "op" : op, "readDest" : readDestCode }
1144 for reg in range(4):
1145 eWalkCode += '''

1146 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

1146 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

1147 ''' % { "reg" : reg }
1148 iop = InstObjParams(name, Name,
1149 "RegRegImmOp",
1150 { "code": eWalkCode,
1151 "r_count": 2,
1152 "predicate_test": predicateTest,
1153 "op_class": opClass }, [])
1154 header_output += NeonRegRegImmOpDeclare.subst(iop)

--- 5 unchanged lines hidden (view full) ---

1160
1161 def twoRegMiscInst(name, Name, opClass, types, rCount, op, readDest=False):
1162 global header_output, exec_output
1163 eWalkCode = simdEnabledCheckCode + '''
1164 RegVect srcReg1, destReg;
1165 '''
1166 for reg in range(rCount):
1167 eWalkCode += '''

1168 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);

1168 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);

1169 ''' % { "reg" : reg }
1170 if readDest:
1171 eWalkCode += '''

1172 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1172 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1173 ''' % { "reg" : reg }
1174 readDestCode = ''
1175 if readDest:
1176 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
1177 eWalkCode += '''
1178 for (unsigned i = 0; i < eCount; i++) {
1179 unsigned j = i;
1180 Element srcElem1 = gtoh(srcReg1.elements[i]);
1181 Element destElem;
1182 %(readDest)s
1183 %(op)s
1184 destReg.elements[j] = htog(destElem);
1185 }
1186 ''' % { "op" : op, "readDest" : readDestCode }
1187 for reg in range(rCount):
1188 eWalkCode += '''

1189 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

1189 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

1190 ''' % { "reg" : reg }
1191 iop = InstObjParams(name, Name,
1192 "RegRegOp",
1193 { "code": eWalkCode,
1194 "r_count": rCount,
1195 "predicate_test": predicateTest,
1196 "op_class": opClass }, [])
1197 header_output += NeonRegRegOpDeclare.subst(iop)

--- 5 unchanged lines hidden (view full) ---

1203
1204 def twoRegMiscScInst(name, Name, opClass, types, rCount, op, readDest=False):
1205 global header_output, exec_output
1206 eWalkCode = simdEnabledCheckCode + '''
1207 RegVect srcReg1, destReg;
1208 '''
1209 for reg in range(rCount):
1210 eWalkCode += '''

1211 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);

1211 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);

1212 ''' % { "reg" : reg }
1213 if readDest:
1214 eWalkCode += '''

1215 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1215 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1216 ''' % { "reg" : reg }
1217 readDestCode = ''
1218 if readDest:
1219 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
1220 eWalkCode += '''
1221 for (unsigned i = 0; i < eCount; i++) {
1222 Element srcElem1 = gtoh(srcReg1.elements[imm]);
1223 Element destElem;
1224 %(readDest)s
1225 %(op)s
1226 destReg.elements[i] = htog(destElem);
1227 }
1228 ''' % { "op" : op, "readDest" : readDestCode }
1229 for reg in range(rCount):
1230 eWalkCode += '''

1231 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

1231 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

1232 ''' % { "reg" : reg }
1233 iop = InstObjParams(name, Name,
1234 "RegRegImmOp",
1235 { "code": eWalkCode,
1236 "r_count": rCount,
1237 "predicate_test": predicateTest,
1238 "op_class": opClass }, [])
1239 header_output += NeonRegRegImmOpDeclare.subst(iop)

--- 5 unchanged lines hidden (view full) ---

1245
1246 def twoRegMiscScramble(name, Name, opClass, types, rCount, op, readDest=False):
1247 global header_output, exec_output
1248 eWalkCode = simdEnabledCheckCode + '''
1249 RegVect srcReg1, destReg;
1250 '''
1251 for reg in range(rCount):
1252 eWalkCode += '''

1253 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1254 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1253 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
1254 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1255 ''' % { "reg" : reg }
1256 if readDest:
1257 eWalkCode += '''
1258 ''' % { "reg" : reg }
1259 readDestCode = ''
1260 if readDest:
1261 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
1262 eWalkCode += op
1263 for reg in range(rCount):
1264 eWalkCode += '''

1265 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
1266 FpOp1P%(reg)d.uw = gtoh(srcReg1.regs[%(reg)d]);

1265 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
1266 FpOp1P%(reg)d_uw = gtoh(srcReg1.regs[%(reg)d]);

1267 ''' % { "reg" : reg }
1268 iop = InstObjParams(name, Name,
1269 "RegRegOp",
1270 { "code": eWalkCode,
1271 "r_count": rCount,
1272 "predicate_test": predicateTest,
1273 "op_class": opClass }, [])
1274 header_output += NeonRegRegOpDeclare.subst(iop)

--- 45 unchanged lines hidden (view full) ---

1320 }
1321 ''' % { "op" : op,
1322 "readDest" : readDestCode,
1323 "destType" : destType,
1324 "writeDest" : writeDest }
1325 for reg in range(rCount):
1326 if toInt:
1327 eWalkCode += '''

1328 FpDestP%(reg)d.uw = destRegs.regs[%(reg)d];

1328 FpDestP%(reg)d_uw = destRegs.regs[%(reg)d];

1329 ''' % { "reg" : reg }
1330 else:
1331 eWalkCode += '''
1332 FpDestP%(reg)d = destRegs[%(reg)d];
1333 ''' % { "reg" : reg }
1334 iop = InstObjParams(name, Name,
1335 "FpRegRegOp",
1336 { "code": eWalkCode,

--- 10 unchanged lines hidden (view full) ---

1347 def twoRegCondenseInst(name, Name, opClass, types, rCount, op, readDest=False):
1348 global header_output, exec_output
1349 eWalkCode = simdEnabledCheckCode + '''
1350 RegVect srcRegs;
1351 BigRegVect destReg;
1352 '''
1353 for reg in range(rCount):
1354 eWalkCode += '''

1355 srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);

1355 srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);

1356 ''' % { "reg" : reg }
1357 if readDest:
1358 eWalkCode += '''

1359 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1359 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1360 ''' % { "reg" : reg }
1361 readDestCode = ''
1362 if readDest:
1363 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
1364 eWalkCode += '''
1365 for (unsigned i = 0; i < eCount / 2; i++) {
1366 Element srcElem1 = gtoh(srcRegs.elements[2 * i]);
1367 Element srcElem2 = gtoh(srcRegs.elements[2 * i + 1]);
1368 BigElement destElem;
1369 %(readDest)s
1370 %(op)s
1371 destReg.elements[i] = htog(destElem);
1372 }
1373 ''' % { "op" : op, "readDest" : readDestCode }
1374 for reg in range(rCount):
1375 eWalkCode += '''

1376 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

1376 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

1377 ''' % { "reg" : reg }
1378 iop = InstObjParams(name, Name,
1379 "RegRegOp",
1380 { "code": eWalkCode,
1381 "r_count": rCount,
1382 "predicate_test": predicateTest,
1383 "op_class": opClass }, [])
1384 header_output += NeonRegRegOpDeclare.subst(iop)

--- 6 unchanged lines hidden (view full) ---

1391 def twoRegNarrowMiscInst(name, Name, opClass, types, op, readDest=False):
1392 global header_output, exec_output
1393 eWalkCode = simdEnabledCheckCode + '''
1394 BigRegVect srcReg1;
1395 RegVect destReg;
1396 '''
1397 for reg in range(4):
1398 eWalkCode += '''

1399 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);

1399 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);

1400 ''' % { "reg" : reg }
1401 if readDest:
1402 for reg in range(2):
1403 eWalkCode += '''

1404 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1404 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1405 ''' % { "reg" : reg }
1406 readDestCode = ''
1407 if readDest:
1408 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
1409 eWalkCode += '''
1410 for (unsigned i = 0; i < eCount; i++) {
1411 BigElement srcElem1 = gtoh(srcReg1.elements[i]);
1412 Element destElem;
1413 %(readDest)s
1414 %(op)s
1415 destReg.elements[i] = htog(destElem);
1416 }
1417 ''' % { "op" : op, "readDest" : readDestCode }
1418 for reg in range(2):
1419 eWalkCode += '''

1420 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

1420 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

1421 ''' % { "reg" : reg }
1422 iop = InstObjParams(name, Name,
1423 "RegRegOp",
1424 { "code": eWalkCode,
1425 "r_count": 2,
1426 "predicate_test": predicateTest,
1427 "op_class": opClass }, [])
1428 header_output += NeonRegRegOpDeclare.subst(iop)

--- 6 unchanged lines hidden (view full) ---

1435 def oneRegImmInst(name, Name, opClass, types, rCount, op, readDest=False):
1436 global header_output, exec_output
1437 eWalkCode = simdEnabledCheckCode + '''
1438 RegVect destReg;
1439 '''
1440 if readDest:
1441 for reg in range(rCount):
1442 eWalkCode += '''

1443 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1443 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1444 ''' % { "reg" : reg }
1445 readDestCode = ''
1446 if readDest:
1447 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
1448 eWalkCode += '''
1449 for (unsigned i = 0; i < eCount; i++) {
1450 Element destElem;
1451 %(readDest)s
1452 %(op)s
1453 destReg.elements[i] = htog(destElem);
1454 }
1455 ''' % { "op" : op, "readDest" : readDestCode }
1456 for reg in range(rCount):
1457 eWalkCode += '''

1458 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

1458 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

1459 ''' % { "reg" : reg }
1460 iop = InstObjParams(name, Name,
1461 "RegImmOp",
1462 { "code": eWalkCode,
1463 "r_count": rCount,
1464 "predicate_test": predicateTest,
1465 "op_class": opClass }, [])
1466 header_output += NeonRegImmOpDeclare.subst(iop)

--- 6 unchanged lines hidden (view full) ---

1473 def twoRegLongMiscInst(name, Name, opClass, types, op, readDest=False):
1474 global header_output, exec_output
1475 eWalkCode = simdEnabledCheckCode + '''
1476 RegVect srcReg1;
1477 BigRegVect destReg;
1478 '''
1479 for reg in range(2):
1480 eWalkCode += '''

1481 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);

1481 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);

1482 ''' % { "reg" : reg }
1483 if readDest:
1484 for reg in range(4):
1485 eWalkCode += '''

1486 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);

1486 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);

1487 ''' % { "reg" : reg }
1488 readDestCode = ''
1489 if readDest:
1490 readDestCode = 'destReg = gtoh(destReg.elements[i]);'
1491 eWalkCode += '''
1492 for (unsigned i = 0; i < eCount; i++) {
1493 Element srcElem1 = gtoh(srcReg1.elements[i]);
1494 BigElement destElem;
1495 %(readDest)s
1496 %(op)s
1497 destReg.elements[i] = htog(destElem);
1498 }
1499 ''' % { "op" : op, "readDest" : readDestCode }
1500 for reg in range(4):
1501 eWalkCode += '''

1502 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

1502 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

1503 ''' % { "reg" : reg }
1504 iop = InstObjParams(name, Name,
1505 "RegRegOp",
1506 { "code": eWalkCode,
1507 "r_count": 2,
1508 "predicate_test": predicateTest,
1509 "op_class": opClass }, [])
1510 header_output += NeonRegRegOpDeclare.subst(iop)

--- 1674 unchanged lines hidden (view full) ---

3185 eWalkCode = '''
3186 RegVect destReg;
3187 for (unsigned i = 0; i < eCount; i++) {
3188 destReg.elements[i] = htog((Element)Op1);
3189 }
3190 '''
3191 for reg in range(rCount):
3192 eWalkCode += '''

3193 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

3193 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

3194 ''' % { "reg" : reg }
3195 iop = InstObjParams(name, Name,
3196 "RegRegOp",
3197 { "code": eWalkCode,
3198 "r_count": rCount,
3199 "predicate_test": predicateTest,
3200 "op_class": opClass }, [])
3201 header_output += NeonRegRegOpDeclare.subst(iop)

--- 63 unchanged lines hidden (view full) ---

3265
3266 def buildVext(name, Name, opClass, types, rCount, op):
3267 global header_output, exec_output
3268 eWalkCode = '''
3269 RegVect srcReg1, srcReg2, destReg;
3270 '''
3271 for reg in range(rCount):
3272 eWalkCode += simdEnabledCheckCode + '''

3273 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
3274 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);

3273 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
3274 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);

3275 ''' % { "reg" : reg }
3276 eWalkCode += op
3277 for reg in range(rCount):
3278 eWalkCode += '''

3279 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);

3279 FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);

3280 ''' % { "reg" : reg }
3281 iop = InstObjParams(name, Name,
3282 "RegRegRegImmOp",
3283 { "code": eWalkCode,
3284 "r_count": rCount,
3285 "predicate_test": predicateTest,
3286 "op_class": opClass }, [])
3287 header_output += NeonRegRegRegImmOpDeclare.subst(iop)

--- 37 unchanged lines hidden (view full) ---

3325 {
3326 uint8_t bytes[8];
3327 FloatRegBits regs[2];
3328 } destReg, srcReg2;
3329
3330 const unsigned length = %(length)d;
3331 const bool isVtbl = %(isVtbl)s;
3332

3333 srcReg2.regs[0] = htog(FpOp2P0.uw);
3334 srcReg2.regs[1] = htog(FpOp2P1.uw);

3333 srcReg2.regs[0] = htog(FpOp2P0_uw);
3334 srcReg2.regs[1] = htog(FpOp2P1_uw);

3335

3336 destReg.regs[0] = htog(FpDestP0.uw);
3337 destReg.regs[1] = htog(FpDestP1.uw);

3336 destReg.regs[0] = htog(FpDestP0_uw);
3337 destReg.regs[1] = htog(FpDestP1_uw);

3338 ''' % { "length" : length, "isVtbl" : isVtbl }
3339 for reg in range(8):
3340 if reg < length * 2:

3341 code += 'table.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);\n' % \

3341 code += 'table.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);\n' % \

3342 { "reg" : reg }
3343 else:
3344 code += 'table.regs[%(reg)d] = 0;\n' % { "reg" : reg }
3345 code += '''
3346 for (unsigned i = 0; i < sizeof(destReg); i++) {
3347 uint8_t index = srcReg2.bytes[i];
3348 if (index < 8 * length) {
3349 destReg.bytes[i] = table.bytes[index];
3350 } else {
3351 if (isVtbl)
3352 destReg.bytes[i] = 0;
3353 // else destReg.bytes[i] unchanged
3354 }
3355 }
3356

3357 FpDestP0.uw = gtoh(destReg.regs[0]);
3358 FpDestP1.uw = gtoh(destReg.regs[1]);

3357 FpDestP0_uw = gtoh(destReg.regs[0]);
3358 FpDestP1_uw = gtoh(destReg.regs[1]);