neon.isa (7853:69aae4379062) neon.isa (8206:c3090dc00ddf)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1756 } else {
1757 if (shiftAmt >= sizeof(Element) * 8) {
1758 destElem = 0;
1759 } else {
1760 destElem = srcElem1 << shiftAmt;
1761 }
1762 }
1763 '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1756 } else {
1757 if (shiftAmt >= sizeof(Element) * 8) {
1758 destElem = 0;
1759 } else {
1760 destElem = srcElem1 << shiftAmt;
1761 }
1762 }
1763 '''
1764 threeEqualRegInst("vshl", "VshlD", "SimdAluOp", allTypes, 2, vshlCode)
1765 threeEqualRegInst("vshl", "VshlQ", "SimdAluOp", allTypes, 4, vshlCode)
1764 threeEqualRegInst("vshl", "VshlD", "SimdShiftOp", allTypes, 2, vshlCode)
1765 threeEqualRegInst("vshl", "VshlQ", "SimdShiftOp", allTypes, 4, vshlCode)
1766
1767 vrshlCode = '''
1768 int16_t shiftAmt = (int8_t)srcElem2;
1769 if (shiftAmt < 0) {
1770 shiftAmt = -shiftAmt;
1771 Element rBit = 0;
1772 if (shiftAmt <= sizeof(Element) * 8)
1773 rBit = bits(srcElem1, shiftAmt - 1);

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3199 "predicate_test": predicateTest,
3200 "op_class": opClass }, [])
3201 header_output += NeonRegRegOpDeclare.subst(iop)
3202 exec_output += NeonEqualRegExecute.subst(iop)
3203 for type in types:
3204 substDict = { "targs" : type,
3205 "class_name" : Name }
3206 exec_output += NeonExecDeclare.subst(substDict)
1766
1767 vrshlCode = '''
1768 int16_t shiftAmt = (int8_t)srcElem2;
1769 if (shiftAmt < 0) {
1770 shiftAmt = -shiftAmt;
1771 Element rBit = 0;
1772 if (shiftAmt <= sizeof(Element) * 8)
1773 rBit = bits(srcElem1, shiftAmt - 1);

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3199 "predicate_test": predicateTest,
3200 "op_class": opClass }, [])
3201 header_output += NeonRegRegOpDeclare.subst(iop)
3202 exec_output += NeonEqualRegExecute.subst(iop)
3203 for type in types:
3204 substDict = { "targs" : type,
3205 "class_name" : Name }
3206 exec_output += NeonExecDeclare.subst(substDict)
3207 vdupGprInst("vdup", "NVdupDGpr", "SimdAluOp", smallUnsignedTypes, 2)
3208 vdupGprInst("vdup", "NVdupQGpr", "SimdAluOp", smallUnsignedTypes, 4)
3207 vdupGprInst("vdup", "NVdupDGpr", "SimdMiscOp", smallUnsignedTypes, 2)
3208 vdupGprInst("vdup", "NVdupQGpr", "SimdMiscOp", smallUnsignedTypes, 4)
3209
3210 vmovCode = 'destElem = imm;'
3211 oneRegImmInst("vmov", "NVmoviD", "SimdMiscOp", ("uint64_t",), 2, vmovCode)
3212 oneRegImmInst("vmov", "NVmoviQ", "SimdMiscOp", ("uint64_t",), 4, vmovCode)
3213
3214 vorrCode = 'destElem |= imm;'
3215 oneRegImmInst("vorr", "NVorriD", "SimdAluOp", ("uint64_t",), 2, vorrCode, True)
3216 oneRegImmInst("vorr", "NVorriQ", "SimdAluOp", ("uint64_t",), 4, vorrCode, True)

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3304#else
3305 fault = new UndefinedInstruction(false, mnemonic);
3306#endif
3307 else
3308 destReg.elements[i] = srcReg2.elements[index];
3309 }
3310 }
3311 '''
3209
3210 vmovCode = 'destElem = imm;'
3211 oneRegImmInst("vmov", "NVmoviD", "SimdMiscOp", ("uint64_t",), 2, vmovCode)
3212 oneRegImmInst("vmov", "NVmoviQ", "SimdMiscOp", ("uint64_t",), 4, vmovCode)
3213
3214 vorrCode = 'destElem |= imm;'
3215 oneRegImmInst("vorr", "NVorriD", "SimdAluOp", ("uint64_t",), 2, vorrCode, True)
3216 oneRegImmInst("vorr", "NVorriQ", "SimdAluOp", ("uint64_t",), 4, vorrCode, True)

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3304#else
3305 fault = new UndefinedInstruction(false, mnemonic);
3306#endif
3307 else
3308 destReg.elements[i] = srcReg2.elements[index];
3309 }
3310 }
3311 '''
3312 buildVext("vext", "NVextD", "SimdAluOp", ("uint8_t",), 2, vextCode)
3313 buildVext("vext", "NVextQ", "SimdAluOp", ("uint8_t",), 4, vextCode)
3312 buildVext("vext", "NVextD", "SimdMiscOp", ("uint8_t",), 2, vextCode)
3313 buildVext("vext", "NVextQ", "SimdMiscOp", ("uint8_t",), 4, vextCode)
3314
3315 def buildVtbxl(name, Name, opClass, length, isVtbl):
3316 global header_output, decoder_output, exec_output
3317 code = '''
3318 union
3319 {
3320 uint8_t bytes[32];
3321 FloatRegBits regs[8];

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3361 "RegRegRegOp",
3362 { "code": code,
3363 "predicate_test": predicateTest,
3364 "op_class": opClass }, [])
3365 header_output += RegRegRegOpDeclare.subst(iop)
3366 decoder_output += RegRegRegOpConstructor.subst(iop)
3367 exec_output += PredOpExecute.subst(iop)
3368
3314
3315 def buildVtbxl(name, Name, opClass, length, isVtbl):
3316 global header_output, decoder_output, exec_output
3317 code = '''
3318 union
3319 {
3320 uint8_t bytes[32];
3321 FloatRegBits regs[8];

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3361 "RegRegRegOp",
3362 { "code": code,
3363 "predicate_test": predicateTest,
3364 "op_class": opClass }, [])
3365 header_output += RegRegRegOpDeclare.subst(iop)
3366 decoder_output += RegRegRegOpConstructor.subst(iop)
3367 exec_output += PredOpExecute.subst(iop)
3368
3369 buildVtbxl("vtbl", "NVtbl1", "SimdAluOp", 1, "true")
3370 buildVtbxl("vtbl", "NVtbl2", "SimdAluOp", 2, "true")
3371 buildVtbxl("vtbl", "NVtbl3", "SimdAluOp", 3, "true")
3372 buildVtbxl("vtbl", "NVtbl4", "SimdAluOp", 4, "true")
3369 buildVtbxl("vtbl", "NVtbl1", "SimdMiscOp", 1, "true")
3370 buildVtbxl("vtbl", "NVtbl2", "SimdMiscOp", 2, "true")
3371 buildVtbxl("vtbl", "NVtbl3", "SimdMiscOp", 3, "true")
3372 buildVtbxl("vtbl", "NVtbl4", "SimdMiscOp", 4, "true")
3373
3373
3374 buildVtbxl("vtbx", "NVtbx1", "SimdAluOp", 1, "false")
3375 buildVtbxl("vtbx", "NVtbx2", "SimdAluOp", 2, "false")
3376 buildVtbxl("vtbx", "NVtbx3", "SimdAluOp", 3, "false")
3377 buildVtbxl("vtbx", "NVtbx4", "SimdAluOp", 4, "false")
3374 buildVtbxl("vtbx", "NVtbx1", "SimdMiscOp", 1, "false")
3375 buildVtbxl("vtbx", "NVtbx2", "SimdMiscOp", 2, "false")
3376 buildVtbxl("vtbx", "NVtbx3", "SimdMiscOp", 3, "false")
3377 buildVtbxl("vtbx", "NVtbx4", "SimdMiscOp", 4, "false")
3378}};
3378}};