neon.isa (7783:9b880b40ac10) neon.isa (7853:69aae4379062)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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866 if readDest:
867 eWalkCode += '''
868 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
869 ''' % { "reg" : reg }
870 readDestCode = ''
871 if readDest:
872 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
873 eWalkCode += '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 857 unchanged lines hidden (view full) ---

866 if readDest:
867 eWalkCode += '''
868 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
869 ''' % { "reg" : reg }
870 readDestCode = ''
871 if readDest:
872 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
873 eWalkCode += '''
874 assert(imm >= 0 && imm < eCount);
875 for (unsigned i = 0; i < eCount; i++) {
876 Element srcElem1 = gtoh(srcReg1.elements[i]);
877 Element srcElem2 = gtoh(srcReg2.elements[imm]);
878 Element destElem;
879 %(readDest)s
880 %(op)s
881 destReg.elements[i] = htog(destElem);
874 if (imm < 0 && imm >= eCount) {
875#if FULL_SYSTEM
876 fault = new UndefinedInstruction;
877#else
878 fault = new UndefinedInstruction(false, mnemonic);
879#endif
880 } else {
881 for (unsigned i = 0; i < eCount; i++) {
882 Element srcElem1 = gtoh(srcReg1.elements[i]);
883 Element srcElem2 = gtoh(srcReg2.elements[imm]);
884 Element destElem;
885 %(readDest)s
886 %(op)s
887 destReg.elements[i] = htog(destElem);
888 }
882 }
883 ''' % { "op" : op, "readDest" : readDestCode }
884 for reg in range(rCount):
885 eWalkCode += '''
886 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
887 ''' % { "reg" : reg }
888 iop = InstObjParams(name, Name,
889 "RegRegRegImmOp",

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914 for reg in range(2 * rCount):
915 eWalkCode += '''
916 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
917 ''' % { "reg" : reg }
918 readDestCode = ''
919 if readDest:
920 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
921 eWalkCode += '''
889 }
890 ''' % { "op" : op, "readDest" : readDestCode }
891 for reg in range(rCount):
892 eWalkCode += '''
893 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
894 ''' % { "reg" : reg }
895 iop = InstObjParams(name, Name,
896 "RegRegRegImmOp",

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921 for reg in range(2 * rCount):
922 eWalkCode += '''
923 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
924 ''' % { "reg" : reg }
925 readDestCode = ''
926 if readDest:
927 readDestCode = 'destElem = gtoh(destReg.elements[i]);'
928 eWalkCode += '''
922 assert(imm >= 0 && imm < eCount);
923 for (unsigned i = 0; i < eCount; i++) {
924 Element srcElem1 = gtoh(srcReg1.elements[i]);
925 Element srcElem2 = gtoh(srcReg2.elements[imm]);
926 BigElement destElem;
927 %(readDest)s
928 %(op)s
929 destReg.elements[i] = htog(destElem);
929 if (imm < 0 && imm >= eCount) {
930#if FULL_SYSTEM
931 fault = new UndefinedInstruction;
932#else
933 fault = new UndefinedInstruction(false, mnemonic);
934#endif
935 } else {
936 for (unsigned i = 0; i < eCount; i++) {
937 Element srcElem1 = gtoh(srcReg1.elements[i]);
938 Element srcElem2 = gtoh(srcReg2.elements[imm]);
939 BigElement destElem;
940 %(readDest)s
941 %(op)s
942 destReg.elements[i] = htog(destElem);
943 }
930 }
931 ''' % { "op" : op, "readDest" : readDestCode }
932 for reg in range(2 * rCount):
933 eWalkCode += '''
934 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
935 ''' % { "reg" : reg }
936 iop = InstObjParams(name, Name,
937 "RegRegRegImmOp",

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960 if readDest:
961 eWalkCode += '''
962 destRegs[%(reg)d] = FpDestP%(reg)d;
963 ''' % { "reg" : reg }
964 readDestCode = ''
965 if readDest:
966 readDestCode = 'destReg = destRegs[i];'
967 eWalkCode += '''
944 }
945 ''' % { "op" : op, "readDest" : readDestCode }
946 for reg in range(2 * rCount):
947 eWalkCode += '''
948 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
949 ''' % { "reg" : reg }
950 iop = InstObjParams(name, Name,
951 "RegRegRegImmOp",

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974 if readDest:
975 eWalkCode += '''
976 destRegs[%(reg)d] = FpDestP%(reg)d;
977 ''' % { "reg" : reg }
978 readDestCode = ''
979 if readDest:
980 readDestCode = 'destReg = destRegs[i];'
981 eWalkCode += '''
968 assert(imm >= 0 && imm < rCount);
969 for (unsigned i = 0; i < rCount; i++) {
970 FloatReg srcReg1 = srcRegs1[i];
971 FloatReg srcReg2 = srcRegs2[imm];
972 FloatReg destReg;
973 %(readDest)s
974 %(op)s
975 destRegs[i] = destReg;
982 if (imm < 0 && imm >= eCount) {
983#if FULL_SYSTEM
984 fault = new UndefinedInstruction;
985#else
986 fault = new UndefinedInstruction(false, mnemonic);
987#endif
988 } else {
989 for (unsigned i = 0; i < rCount; i++) {
990 FloatReg srcReg1 = srcRegs1[i];
991 FloatReg srcReg2 = srcRegs2[imm];
992 FloatReg destReg;
993 %(readDest)s
994 %(op)s
995 destRegs[i] = destReg;
996 }
976 }
977 ''' % { "op" : op, "readDest" : readDestCode }
978 for reg in range(rCount):
979 eWalkCode += '''
980 FpDestP%(reg)d = destRegs[%(reg)d];
981 ''' % { "reg" : reg }
982 iop = InstObjParams(name, Name,
983 "FpRegRegRegImmOp",

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3272
3273 vextCode = '''
3274 for (unsigned i = 0; i < eCount; i++) {
3275 unsigned index = i + imm;
3276 if (index < eCount) {
3277 destReg.elements[i] = srcReg1.elements[index];
3278 } else {
3279 index -= eCount;
997 }
998 ''' % { "op" : op, "readDest" : readDestCode }
999 for reg in range(rCount):
1000 eWalkCode += '''
1001 FpDestP%(reg)d = destRegs[%(reg)d];
1002 ''' % { "reg" : reg }
1003 iop = InstObjParams(name, Name,
1004 "FpRegRegRegImmOp",

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3293
3294 vextCode = '''
3295 for (unsigned i = 0; i < eCount; i++) {
3296 unsigned index = i + imm;
3297 if (index < eCount) {
3298 destReg.elements[i] = srcReg1.elements[index];
3299 } else {
3300 index -= eCount;
3280 assert(index < eCount);
3281 destReg.elements[i] = srcReg2.elements[index];
3301 if (index >= eCount)
3302#if FULL_SYSTEM
3303 fault = new UndefinedInstruction;
3304#else
3305 fault = new UndefinedInstruction(false, mnemonic);
3306#endif
3307 else
3308 destReg.elements[i] = srcReg2.elements[index];
3282 }
3283 }
3284 '''
3285 buildVext("vext", "NVextD", "SimdAluOp", ("uint8_t",), 2, vextCode)
3286 buildVext("vext", "NVextQ", "SimdAluOp", ("uint8_t",), 4, vextCode)
3287
3288 def buildVtbxl(name, Name, opClass, length, isVtbl):
3289 global header_output, decoder_output, exec_output

--- 62 unchanged lines hidden --- 		3309 }
3310 }
3311 '''
3312 buildVext("vext", "NVextD", "SimdAluOp", ("uint8_t",), 2, vextCode)
3313 buildVext("vext", "NVextQ", "SimdAluOp", ("uint8_t",), 4, vextCode)
3314
3315 def buildVtbxl(name, Name, opClass, length, isVtbl):
3316 global header_output, decoder_output, exec_output

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