neon.isa (7641:788c719d0fc8) neon.isa (7644:62873d5c2bfc)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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615 {
616 if (isSnan(op1) || isSnan(op2))
617 return 2.0;
618 return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0;
619 }
620}};
621
622let {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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615 {
616 if (isSnan(op1) || isSnan(op2))
617 return 2.0;
618 return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0;
619 }
620}};
621
622let {{
623 simdEnabledCheckCode = '''
624 if (!neonEnabled(Cpacr, Cpsr, Fpexc))
625 return disabledFault();
626 '''
627}};
628
623
629let {{
630
631 header_output = ""
632 exec_output = ""
633
634 smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t")
635 unsignedTypes = smallUnsignedTypes + ("uint64_t",)
636 smallSignedTypes = ("int8_t", "int16_t", "int32_t")
637 signedTypes = smallSignedTypes + ("int64_t",)
638 smallTypes = smallUnsignedTypes + smallSignedTypes

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3230 smallSignedTypes, vqmovunsCode)
3231
3232 def buildVext(name, Name, types, rCount, op):
3233 global header_output, exec_output
3234 eWalkCode = '''
3235 RegVect srcReg1, srcReg2, destReg;
3236 '''
3237 for reg in range(rCount):
624 header_output = ""
625 exec_output = ""
626
627 smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t")
628 unsignedTypes = smallUnsignedTypes + ("uint64_t",)
629 smallSignedTypes = ("int8_t", "int16_t", "int32_t")
630 signedTypes = smallSignedTypes + ("int64_t",)
631 smallTypes = smallUnsignedTypes + smallSignedTypes

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3223 smallSignedTypes, vqmovunsCode)
3224
3225 def buildVext(name, Name, types, rCount, op):
3226 global header_output, exec_output
3227 eWalkCode = '''
3228 RegVect srcReg1, srcReg2, destReg;
3229 '''
3230 for reg in range(rCount):
3238 eWalkCode += '''
3231 eWalkCode += simdEnabledCheckCode + '''
3239 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
3240 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
3241 ''' % { "reg" : reg }
3242 eWalkCode += op
3243 for reg in range(rCount):
3244 eWalkCode += '''
3245 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
3246 ''' % { "reg" : reg }

--- 90 unchanged lines hidden --- 		3232 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
3233 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
3234 ''' % { "reg" : reg }
3235 eWalkCode += op
3236 for reg in range(rCount):
3237 eWalkCode += '''
3238 FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
3239 ''' % { "reg" : reg }

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