neon.isa (7639:8c09b7ff5b57) neon.isa (7640:5286a8a469c5)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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615 {
616 if (isSnan(op1) || isSnan(op2))
617 return 2.0;
618 return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0;
619 }
620}};
621
622let {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 606 unchanged lines hidden (view full) ---

615 {
616 if (isSnan(op1) || isSnan(op2))
617 return 2.0;
618 return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0;
619 }
620}};
621
622let {{
623 simdEnabledCheckCode = '''
624 if (!neonEnabled(Cpacr, Cpsr, Fpexc))
625 return disabledFault();
626 '''
627}};
623
628
629let {{
630
624 header_output = ""
625 exec_output = ""
626
627 smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t")
628 unsignedTypes = smallUnsignedTypes + ("uint64_t",)
629 smallSignedTypes = ("int8_t", "int16_t", "int32_t")
630 signedTypes = smallSignedTypes + ("int64_t",)
631 smallTypes = smallUnsignedTypes + smallSignedTypes
632 allTypes = unsignedTypes + signedTypes
633
634 def threeEqualRegInst(name, Name, types, rCount, op,
635 readDest=False, pairwise=False):
636 global header_output, exec_output
631 header_output = ""
632 exec_output = ""
633
634 smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t")
635 unsignedTypes = smallUnsignedTypes + ("uint64_t",)
636 smallSignedTypes = ("int8_t", "int16_t", "int32_t")
637 signedTypes = smallSignedTypes + ("int64_t",)
638 smallTypes = smallUnsignedTypes + smallSignedTypes
639 allTypes = unsignedTypes + signedTypes
640
641 def threeEqualRegInst(name, Name, types, rCount, op,
642 readDest=False, pairwise=False):
643 global header_output, exec_output
637 eWalkCode = '''
644 eWalkCode = simdEnabledCheckCode + '''
638 RegVect srcReg1, srcReg2, destReg;
639 '''
640 for reg in range(rCount):
641 eWalkCode += '''
642 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
643 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
644 ''' % { "reg" : reg }
645 if readDest:

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689 for type in types:
690 substDict = { "targs" : type,
691 "class_name" : Name }
692 exec_output += NeonExecDeclare.subst(substDict)
693
694 def threeEqualRegInstFp(name, Name, types, rCount, op,
695 readDest=False, pairwise=False, toInt=False):
696 global header_output, exec_output
645 RegVect srcReg1, srcReg2, destReg;
646 '''
647 for reg in range(rCount):
648 eWalkCode += '''
649 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
650 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
651 ''' % { "reg" : reg }
652 if readDest:

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696 for type in types:
697 substDict = { "targs" : type,
698 "class_name" : Name }
699 exec_output += NeonExecDeclare.subst(substDict)
700
701 def threeEqualRegInstFp(name, Name, types, rCount, op,
702 readDest=False, pairwise=False, toInt=False):
703 global header_output, exec_output
697 eWalkCode = '''
704 eWalkCode = simdEnabledCheckCode + '''
698 typedef FloatReg FloatVect[rCount];
699 FloatVect srcRegs1, srcRegs2;
700 '''
701 if toInt:
702 eWalkCode += 'RegVect destRegs;\n'
703 else:
704 eWalkCode += 'FloatVect destRegs;\n'
705 for reg in range(rCount):

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784 src1Cnt = 4
785 src1Prefix = 'Big'
786 if bigSrc2:
787 src2Cnt = 4
788 src2Prefix = 'Big'
789 if bigDest:
790 destCnt = 4
791 destPrefix = 'Big'
705 typedef FloatReg FloatVect[rCount];
706 FloatVect srcRegs1, srcRegs2;
707 '''
708 if toInt:
709 eWalkCode += 'RegVect destRegs;\n'
710 else:
711 eWalkCode += 'FloatVect destRegs;\n'
712 for reg in range(rCount):

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791 src1Cnt = 4
792 src1Prefix = 'Big'
793 if bigSrc2:
794 src2Cnt = 4
795 src2Prefix = 'Big'
796 if bigDest:
797 destCnt = 4
798 destPrefix = 'Big'
792 eWalkCode = '''
799 eWalkCode = simdEnabledCheckCode + '''
793 %sRegVect srcReg1;
794 %sRegVect srcReg2;
795 %sRegVect destReg;
796 ''' % (src1Prefix, src2Prefix, destPrefix)
797 for reg in range(src1Cnt):
798 eWalkCode += '''
799 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
800 ''' % { "reg" : reg }

--- 46 unchanged lines hidden (view full) ---

847 False, False, True, readDest)
848
849 def threeRegWideInst(name, Name, types, op, readDest=False):
850 threeUnequalRegInst(name, Name, types, op,
851 True, False, True, readDest)
852
853 def twoEqualRegInst(name, Name, types, rCount, op, readDest=False):
854 global header_output, exec_output
800 %sRegVect srcReg1;
801 %sRegVect srcReg2;
802 %sRegVect destReg;
803 ''' % (src1Prefix, src2Prefix, destPrefix)
804 for reg in range(src1Cnt):
805 eWalkCode += '''
806 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
807 ''' % { "reg" : reg }

--- 46 unchanged lines hidden (view full) ---

854 False, False, True, readDest)
855
856 def threeRegWideInst(name, Name, types, op, readDest=False):
857 threeUnequalRegInst(name, Name, types, op,
858 True, False, True, readDest)
859
860 def twoEqualRegInst(name, Name, types, rCount, op, readDest=False):
861 global header_output, exec_output
855 eWalkCode = '''
862 eWalkCode = simdEnabledCheckCode + '''
856 RegVect srcReg1, srcReg2, destReg;
857 '''
858 for reg in range(rCount):
859 eWalkCode += '''
860 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
861 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
862 ''' % { "reg" : reg }
863 if readDest:

--- 28 unchanged lines hidden (view full) ---

892 for type in types:
893 substDict = { "targs" : type,
894 "class_name" : Name }
895 exec_output += NeonExecDeclare.subst(substDict)
896
897 def twoRegLongInst(name, Name, types, op, readDest=False):
898 global header_output, exec_output
899 rCount = 2
863 RegVect srcReg1, srcReg2, destReg;
864 '''
865 for reg in range(rCount):
866 eWalkCode += '''
867 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
868 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
869 ''' % { "reg" : reg }
870 if readDest:

--- 28 unchanged lines hidden (view full) ---

899 for type in types:
900 substDict = { "targs" : type,
901 "class_name" : Name }
902 exec_output += NeonExecDeclare.subst(substDict)
903
904 def twoRegLongInst(name, Name, types, op, readDest=False):
905 global header_output, exec_output
906 rCount = 2
900 eWalkCode = '''
907 eWalkCode = simdEnabledCheckCode + '''
901 RegVect srcReg1, srcReg2;
902 BigRegVect destReg;
903 '''
904 for reg in range(rCount):
905 eWalkCode += '''
906 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
907 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);;
908 ''' % { "reg" : reg }

--- 29 unchanged lines hidden (view full) ---

938 exec_output += NeonUnequalRegExecute.subst(iop)
939 for type in types:
940 substDict = { "targs" : type,
941 "class_name" : Name }
942 exec_output += NeonExecDeclare.subst(substDict)
943
944 def twoEqualRegInstFp(name, Name, types, rCount, op, readDest=False):
945 global header_output, exec_output
908 RegVect srcReg1, srcReg2;
909 BigRegVect destReg;
910 '''
911 for reg in range(rCount):
912 eWalkCode += '''
913 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
914 srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);;
915 ''' % { "reg" : reg }

--- 29 unchanged lines hidden (view full) ---

945 exec_output += NeonUnequalRegExecute.subst(iop)
946 for type in types:
947 substDict = { "targs" : type,
948 "class_name" : Name }
949 exec_output += NeonExecDeclare.subst(substDict)
950
951 def twoEqualRegInstFp(name, Name, types, rCount, op, readDest=False):
952 global header_output, exec_output
946 eWalkCode = '''
953 eWalkCode = simdEnabledCheckCode + '''
947 typedef FloatReg FloatVect[rCount];
948 FloatVect srcRegs1, srcRegs2, destRegs;
949 '''
950 for reg in range(rCount):
951 eWalkCode += '''
952 srcRegs1[%(reg)d] = FpOp1P%(reg)d;
953 srcRegs2[%(reg)d] = FpOp2P%(reg)d;
954 ''' % { "reg" : reg }

--- 29 unchanged lines hidden (view full) ---

984 for type in types:
985 substDict = { "targs" : type,
986 "class_name" : Name }
987 exec_output += NeonExecDeclare.subst(substDict)
988
989 def twoRegShiftInst(name, Name, types, rCount, op,
990 readDest=False, toInt=False, fromInt=False):
991 global header_output, exec_output
954 typedef FloatReg FloatVect[rCount];
955 FloatVect srcRegs1, srcRegs2, destRegs;
956 '''
957 for reg in range(rCount):
958 eWalkCode += '''
959 srcRegs1[%(reg)d] = FpOp1P%(reg)d;
960 srcRegs2[%(reg)d] = FpOp2P%(reg)d;
961 ''' % { "reg" : reg }

--- 29 unchanged lines hidden (view full) ---

991 for type in types:
992 substDict = { "targs" : type,
993 "class_name" : Name }
994 exec_output += NeonExecDeclare.subst(substDict)
995
996 def twoRegShiftInst(name, Name, types, rCount, op,
997 readDest=False, toInt=False, fromInt=False):
998 global header_output, exec_output
992 eWalkCode = '''
999 eWalkCode = simdEnabledCheckCode + '''
993 RegVect srcRegs1, destRegs;
994 '''
995 for reg in range(rCount):
996 eWalkCode += '''
997 srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
998 ''' % { "reg" : reg }
999 if readDest:
1000 eWalkCode += '''

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1039 exec_output += NeonEqualRegExecute.subst(iop)
1040 for type in types:
1041 substDict = { "targs" : type,
1042 "class_name" : Name }
1043 exec_output += NeonExecDeclare.subst(substDict)
1044
1045 def twoRegNarrowShiftInst(name, Name, types, op, readDest=False):
1046 global header_output, exec_output
1000 RegVect srcRegs1, destRegs;
1001 '''
1002 for reg in range(rCount):
1003 eWalkCode += '''
1004 srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1005 ''' % { "reg" : reg }
1006 if readDest:
1007 eWalkCode += '''

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1046 exec_output += NeonEqualRegExecute.subst(iop)
1047 for type in types:
1048 substDict = { "targs" : type,
1049 "class_name" : Name }
1050 exec_output += NeonExecDeclare.subst(substDict)
1051
1052 def twoRegNarrowShiftInst(name, Name, types, op, readDest=False):
1053 global header_output, exec_output
1047 eWalkCode = '''
1054 eWalkCode = simdEnabledCheckCode + '''
1048 BigRegVect srcReg1;
1049 RegVect destReg;
1050 '''
1051 for reg in range(4):
1052 eWalkCode += '''
1053 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1054 ''' % { "reg" : reg }
1055 if readDest:

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1082 exec_output += NeonUnequalRegExecute.subst(iop)
1083 for type in types:
1084 substDict = { "targs" : type,
1085 "class_name" : Name }
1086 exec_output += NeonExecDeclare.subst(substDict)
1087
1088 def twoRegLongShiftInst(name, Name, types, op, readDest=False):
1089 global header_output, exec_output
1055 BigRegVect srcReg1;
1056 RegVect destReg;
1057 '''
1058 for reg in range(4):
1059 eWalkCode += '''
1060 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1061 ''' % { "reg" : reg }
1062 if readDest:

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1089 exec_output += NeonUnequalRegExecute.subst(iop)
1090 for type in types:
1091 substDict = { "targs" : type,
1092 "class_name" : Name }
1093 exec_output += NeonExecDeclare.subst(substDict)
1094
1095 def twoRegLongShiftInst(name, Name, types, op, readDest=False):
1096 global header_output, exec_output
1090 eWalkCode = '''
1097 eWalkCode = simdEnabledCheckCode + '''
1091 RegVect srcReg1;
1092 BigRegVect destReg;
1093 '''
1094 for reg in range(2):
1095 eWalkCode += '''
1096 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1097 ''' % { "reg" : reg }
1098 if readDest:

--- 26 unchanged lines hidden (view full) ---

1125 exec_output += NeonUnequalRegExecute.subst(iop)
1126 for type in types:
1127 substDict = { "targs" : type,
1128 "class_name" : Name }
1129 exec_output += NeonExecDeclare.subst(substDict)
1130
1131 def twoRegMiscInst(name, Name, types, rCount, op, readDest=False):
1132 global header_output, exec_output
1098 RegVect srcReg1;
1099 BigRegVect destReg;
1100 '''
1101 for reg in range(2):
1102 eWalkCode += '''
1103 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1104 ''' % { "reg" : reg }
1105 if readDest:

--- 26 unchanged lines hidden (view full) ---

1132 exec_output += NeonUnequalRegExecute.subst(iop)
1133 for type in types:
1134 substDict = { "targs" : type,
1135 "class_name" : Name }
1136 exec_output += NeonExecDeclare.subst(substDict)
1137
1138 def twoRegMiscInst(name, Name, types, rCount, op, readDest=False):
1139 global header_output, exec_output
1133 eWalkCode = '''
1140 eWalkCode = simdEnabledCheckCode + '''
1134 RegVect srcReg1, destReg;
1135 '''
1136 for reg in range(rCount):
1137 eWalkCode += '''
1138 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1139 ''' % { "reg" : reg }
1140 if readDest:
1141 eWalkCode += '''

--- 25 unchanged lines hidden (view full) ---

1167 exec_output += NeonEqualRegExecute.subst(iop)
1168 for type in types:
1169 substDict = { "targs" : type,
1170 "class_name" : Name }
1171 exec_output += NeonExecDeclare.subst(substDict)
1172
1173 def twoRegMiscScInst(name, Name, types, rCount, op, readDest=False):
1174 global header_output, exec_output
1141 RegVect srcReg1, destReg;
1142 '''
1143 for reg in range(rCount):
1144 eWalkCode += '''
1145 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1146 ''' % { "reg" : reg }
1147 if readDest:
1148 eWalkCode += '''

--- 25 unchanged lines hidden (view full) ---

1174 exec_output += NeonEqualRegExecute.subst(iop)
1175 for type in types:
1176 substDict = { "targs" : type,
1177 "class_name" : Name }
1178 exec_output += NeonExecDeclare.subst(substDict)
1179
1180 def twoRegMiscScInst(name, Name, types, rCount, op, readDest=False):
1181 global header_output, exec_output
1175 eWalkCode = '''
1182 eWalkCode = simdEnabledCheckCode + '''
1176 RegVect srcReg1, destReg;
1177 '''
1178 for reg in range(rCount):
1179 eWalkCode += '''
1180 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1181 ''' % { "reg" : reg }
1182 if readDest:
1183 eWalkCode += '''

--- 24 unchanged lines hidden (view full) ---

1208 exec_output += NeonEqualRegExecute.subst(iop)
1209 for type in types:
1210 substDict = { "targs" : type,
1211 "class_name" : Name }
1212 exec_output += NeonExecDeclare.subst(substDict)
1213
1214 def twoRegMiscScramble(name, Name, types, rCount, op, readDest=False):
1215 global header_output, exec_output
1183 RegVect srcReg1, destReg;
1184 '''
1185 for reg in range(rCount):
1186 eWalkCode += '''
1187 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1188 ''' % { "reg" : reg }
1189 if readDest:
1190 eWalkCode += '''

--- 24 unchanged lines hidden (view full) ---

1215 exec_output += NeonEqualRegExecute.subst(iop)
1216 for type in types:
1217 substDict = { "targs" : type,
1218 "class_name" : Name }
1219 exec_output += NeonExecDeclare.subst(substDict)
1220
1221 def twoRegMiscScramble(name, Name, types, rCount, op, readDest=False):
1222 global header_output, exec_output
1216 eWalkCode = '''
1223 eWalkCode = simdEnabledCheckCode + '''
1217 RegVect srcReg1, destReg;
1218 '''
1219 for reg in range(rCount):
1220 eWalkCode += '''
1221 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1222 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
1223 ''' % { "reg" : reg }
1224 if readDest:

--- 18 unchanged lines hidden (view full) ---

1243 for type in types:
1244 substDict = { "targs" : type,
1245 "class_name" : Name }
1246 exec_output += NeonExecDeclare.subst(substDict)
1247
1248 def twoRegMiscInstFp(name, Name, types, rCount, op,
1249 readDest=False, toInt=False):
1250 global header_output, exec_output
1224 RegVect srcReg1, destReg;
1225 '''
1226 for reg in range(rCount):
1227 eWalkCode += '''
1228 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1229 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
1230 ''' % { "reg" : reg }
1231 if readDest:

--- 18 unchanged lines hidden (view full) ---

1250 for type in types:
1251 substDict = { "targs" : type,
1252 "class_name" : Name }
1253 exec_output += NeonExecDeclare.subst(substDict)
1254
1255 def twoRegMiscInstFp(name, Name, types, rCount, op,
1256 readDest=False, toInt=False):
1257 global header_output, exec_output
1251 eWalkCode = '''
1258 eWalkCode = simdEnabledCheckCode + '''
1252 typedef FloatReg FloatVect[rCount];
1253 FloatVect srcRegs1;
1254 '''
1255 if toInt:
1256 eWalkCode += 'RegVect destRegs;\n'
1257 else:
1258 eWalkCode += 'FloatVect destRegs;\n'
1259 for reg in range(rCount):

--- 47 unchanged lines hidden (view full) ---

1307 exec_output += NeonEqualRegExecute.subst(iop)
1308 for type in types:
1309 substDict = { "targs" : type,
1310 "class_name" : Name }
1311 exec_output += NeonExecDeclare.subst(substDict)
1312
1313 def twoRegCondenseInst(name, Name, types, rCount, op, readDest=False):
1314 global header_output, exec_output
1259 typedef FloatReg FloatVect[rCount];
1260 FloatVect srcRegs1;
1261 '''
1262 if toInt:
1263 eWalkCode += 'RegVect destRegs;\n'
1264 else:
1265 eWalkCode += 'FloatVect destRegs;\n'
1266 for reg in range(rCount):

--- 47 unchanged lines hidden (view full) ---

1314 exec_output += NeonEqualRegExecute.subst(iop)
1315 for type in types:
1316 substDict = { "targs" : type,
1317 "class_name" : Name }
1318 exec_output += NeonExecDeclare.subst(substDict)
1319
1320 def twoRegCondenseInst(name, Name, types, rCount, op, readDest=False):
1321 global header_output, exec_output
1315 eWalkCode = '''
1322 eWalkCode = simdEnabledCheckCode + '''
1316 RegVect srcRegs;
1317 BigRegVect destReg;
1318 '''
1319 for reg in range(rCount):
1320 eWalkCode += '''
1321 srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1322 ''' % { "reg" : reg }
1323 if readDest:

--- 26 unchanged lines hidden (view full) ---

1350 exec_output += NeonUnequalRegExecute.subst(iop)
1351 for type in types:
1352 substDict = { "targs" : type,
1353 "class_name" : Name }
1354 exec_output += NeonExecDeclare.subst(substDict)
1355
1356 def twoRegNarrowMiscInst(name, Name, types, op, readDest=False):
1357 global header_output, exec_output
1323 RegVect srcRegs;
1324 BigRegVect destReg;
1325 '''
1326 for reg in range(rCount):
1327 eWalkCode += '''
1328 srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1329 ''' % { "reg" : reg }
1330 if readDest:

--- 26 unchanged lines hidden (view full) ---

1357 exec_output += NeonUnequalRegExecute.subst(iop)
1358 for type in types:
1359 substDict = { "targs" : type,
1360 "class_name" : Name }
1361 exec_output += NeonExecDeclare.subst(substDict)
1362
1363 def twoRegNarrowMiscInst(name, Name, types, op, readDest=False):
1364 global header_output, exec_output
1358 eWalkCode = '''
1365 eWalkCode = simdEnabledCheckCode + '''
1359 BigRegVect srcReg1;
1360 RegVect destReg;
1361 '''
1362 for reg in range(4):
1363 eWalkCode += '''
1364 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1365 ''' % { "reg" : reg }
1366 if readDest:

--- 26 unchanged lines hidden (view full) ---

1393 exec_output += NeonUnequalRegExecute.subst(iop)
1394 for type in types:
1395 substDict = { "targs" : type,
1396 "class_name" : Name }
1397 exec_output += NeonExecDeclare.subst(substDict)
1398
1399 def oneRegImmInst(name, Name, types, rCount, op, readDest=False):
1400 global header_output, exec_output
1366 BigRegVect srcReg1;
1367 RegVect destReg;
1368 '''
1369 for reg in range(4):
1370 eWalkCode += '''
1371 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1372 ''' % { "reg" : reg }
1373 if readDest:

--- 26 unchanged lines hidden (view full) ---

1400 exec_output += NeonUnequalRegExecute.subst(iop)
1401 for type in types:
1402 substDict = { "targs" : type,
1403 "class_name" : Name }
1404 exec_output += NeonExecDeclare.subst(substDict)
1405
1406 def oneRegImmInst(name, Name, types, rCount, op, readDest=False):
1407 global header_output, exec_output
1401 eWalkCode = '''
1408 eWalkCode = simdEnabledCheckCode + '''
1402 RegVect destReg;
1403 '''
1404 if readDest:
1405 for reg in range(rCount):
1406 eWalkCode += '''
1407 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
1408 ''' % { "reg" : reg }
1409 readDestCode = ''

--- 20 unchanged lines hidden (view full) ---

1430 exec_output += NeonEqualRegExecute.subst(iop)
1431 for type in types:
1432 substDict = { "targs" : type,
1433 "class_name" : Name }
1434 exec_output += NeonExecDeclare.subst(substDict)
1435
1436 def twoRegLongMiscInst(name, Name, types, op, readDest=False):
1437 global header_output, exec_output
1409 RegVect destReg;
1410 '''
1411 if readDest:
1412 for reg in range(rCount):
1413 eWalkCode += '''
1414 destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
1415 ''' % { "reg" : reg }
1416 readDestCode = ''

--- 20 unchanged lines hidden (view full) ---

1437 exec_output += NeonEqualRegExecute.subst(iop)
1438 for type in types:
1439 substDict = { "targs" : type,
1440 "class_name" : Name }
1441 exec_output += NeonExecDeclare.subst(substDict)
1442
1443 def twoRegLongMiscInst(name, Name, types, op, readDest=False):
1444 global header_output, exec_output
1438 eWalkCode = '''
1445 eWalkCode = simdEnabledCheckCode + '''
1439 RegVect srcReg1;
1440 BigRegVect destReg;
1441 '''
1442 for reg in range(2):
1443 eWalkCode += '''
1444 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1445 ''' % { "reg" : reg }
1446 if readDest:

--- 1897 unchanged lines hidden --- 		1446 RegVect srcReg1;
1447 BigRegVect destReg;
1448 '''
1449 for reg in range(2):
1450 eWalkCode += '''
1451 srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
1452 ''' % { "reg" : reg }
1453 if readDest:

--- 1897 unchanged lines hidden ---