Cross Reference: /gem5/src/arch/arm/isa/insts/neon.isa

1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2015 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1191 substDict = { "targs" : type,
1192 "class_name" : Name }
1193 exec_output += NeonExecDeclare.subst(substDict)
1194
1195 def threeEqualRegInstFp(name, Name, opClass, types, rCount, op,
1196 readDest=False, pairwise=False, toInt=False):
1197 global header_output, exec_output
1198 eWalkCode = simdEnabledCheckCode + '''

1199 typedef FloatReg FloatVect[rCount];

1199 typedef float FloatVect[rCount];

1200 FloatVect srcRegs1, srcRegs2;
1201 '''
1202 if toInt:
1203 eWalkCode += 'RegVect destRegs;\n'
1204 else:
1205 eWalkCode += 'FloatVect destRegs;\n'
1206 for reg in range(rCount):
1207 eWalkCode += '''

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1215 ''' % { "reg" : reg }
1216 else:
1217 eWalkCode += '''
1218 destRegs[%(reg)d] = FpDestP%(reg)d;
1219 ''' % { "reg" : reg }
1220 readDestCode = ''
1221 if readDest:
1222 readDestCode = 'destReg = destRegs[r];'

1223 destType = 'FloatReg'

1223 destType = 'float'

1224 writeDest = 'destRegs[r] = destReg;'
1225 if toInt:

1226 destType = 'FloatRegBits'

1226 destType = 'uint32_t'

1227 writeDest = 'destRegs.regs[r] = destReg;'
1228 if pairwise:
1229 eWalkCode += '''
1230 for (unsigned r = 0; r < rCount; r++) {

1231 FloatReg srcReg1 = (2 * r < rCount) ?

1231 float srcReg1 = (2 * r < rCount) ?

1232 srcRegs1[2 * r] : srcRegs2[2 * r - rCount];

1233 FloatReg srcReg2 = (2 * r < rCount) ?

1233 float srcReg2 = (2 * r < rCount) ?

1234 srcRegs1[2 * r + 1] : srcRegs2[2 * r + 1 - rCount];
1235 %(destType)s destReg;
1236 %(readDest)s
1237 %(op)s
1238 %(writeDest)s
1239 }
1240 ''' % { "op" : op,
1241 "readDest" : readDestCode,
1242 "destType" : destType,
1243 "writeDest" : writeDest }
1244 else:
1245 eWalkCode += '''
1246 for (unsigned r = 0; r < rCount; r++) {

1247 FloatReg srcReg1 = srcRegs1[r];
1248 FloatReg srcReg2 = srcRegs2[r];

1247 float srcReg1 = srcRegs1[r];
1248 float srcReg2 = srcRegs2[r];

1249 %(destType)s destReg;
1250 %(readDest)s
1251 %(op)s
1252 %(writeDest)s
1253 }
1254 ''' % { "op" : op,
1255 "readDest" : readDestCode,
1256 "destType" : destType,

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1452 for type in types:
1453 substDict = { "targs" : type,
1454 "class_name" : Name }
1455 exec_output += NeonExecDeclare.subst(substDict)
1456
1457 def twoEqualRegInstFp(name, Name, opClass, types, rCount, op, readDest=False):
1458 global header_output, exec_output
1459 eWalkCode = simdEnabledCheckCode + '''

1460 typedef FloatReg FloatVect[rCount];

1460 typedef float FloatVect[rCount];

1461 FloatVect srcRegs1, srcRegs2, destRegs;
1462 '''
1463 for reg in range(rCount):
1464 eWalkCode += '''
1465 srcRegs1[%(reg)d] = FpOp1P%(reg)d;
1466 srcRegs2[%(reg)d] = FpOp2P%(reg)d;
1467 ''' % { "reg" : reg }
1468 if readDest:

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1473 if readDest:
1474 readDestCode = 'destReg = destRegs[i];'
1475 eWalkCode += '''
1476 if (imm < 0 && imm >= eCount) {
1477 fault = std::make_shared<UndefinedInstruction>(machInst, false,
1478 mnemonic);
1479 } else {
1480 for (unsigned i = 0; i < rCount; i++) {

1481 FloatReg srcReg1 = srcRegs1[i];
1482 FloatReg srcReg2 = srcRegs2[imm];
1483 FloatReg destReg;

1481 float srcReg1 = srcRegs1[i];
1482 float srcReg2 = srcRegs2[imm];
1483 float destReg;

1484 %(readDest)s
1485 %(op)s
1486 destRegs[i] = destReg;
1487 }
1488 }
1489 ''' % { "op" : op, "readDest" : readDestCode }
1490 for reg in range(rCount):
1491 eWalkCode += '''

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1520 ''' % { "reg" : reg }
1521 readDestCode = ''
1522 if readDest:
1523 readDestCode = 'destElem = gtoh(destRegs.elements[i]);'
1524 if toInt:
1525 readDestCode = 'destReg = gtoh(destRegs.regs[i]);'
1526 readOpCode = 'Element srcElem1 = gtoh(srcRegs1.elements[i]);'
1527 if fromInt:

1528 readOpCode = 'FloatRegBits srcReg1 = gtoh(srcRegs1.regs[i]);'

1528 readOpCode = 'uint32_t srcReg1 = gtoh(srcRegs1.regs[i]);'

1529 declDest = 'Element destElem;'
1530 writeDestCode = 'destRegs.elements[i] = htog(destElem);'
1531 if toInt:

1532 declDest = 'FloatRegBits destReg;'

1532 declDest = 'uint32_t destReg;'

1533 writeDestCode = 'destRegs.regs[i] = htog(destReg);'
1534 eWalkCode += '''
1535 for (unsigned i = 0; i < eCount; i++) {
1536 %(readOp)s
1537 %(declDest)s
1538 %(readDest)s
1539 %(op)s
1540 %(writeDest)s

--- 227 unchanged lines hidden (view full) ---

1768 substDict = { "targs" : type,
1769 "class_name" : Name }
1770 exec_output += NeonExecDeclare.subst(substDict)
1771
1772 def twoRegMiscInstFp(name, Name, opClass, types, rCount, op,
1773 readDest=False, toInt=False):
1774 global header_output, exec_output
1775 eWalkCode = simdEnabledCheckCode + '''

1776 typedef FloatReg FloatVect[rCount];

1776 typedef float FloatVect[rCount];

1777 FloatVect srcRegs1;
1778 '''
1779 if toInt:
1780 eWalkCode += 'RegVect destRegs;\n'
1781 else:
1782 eWalkCode += 'FloatVect destRegs;\n'
1783 for reg in range(rCount):
1784 eWalkCode += '''

--- 6 unchanged lines hidden (view full) ---

1791 ''' % { "reg" : reg }
1792 else:
1793 eWalkCode += '''
1794 destRegs[%(reg)d] = FpDestP%(reg)d;
1795 ''' % { "reg" : reg }
1796 readDestCode = ''
1797 if readDest:
1798 readDestCode = 'destReg = destRegs[i];'

1799 destType = 'FloatReg'

1799 destType = 'float'

1800 writeDest = 'destRegs[r] = destReg;'
1801 if toInt:

1802 destType = 'FloatRegBits'

1802 destType = 'uint32_t'

1803 writeDest = 'destRegs.regs[r] = destReg;'
1804 eWalkCode += '''
1805 for (unsigned r = 0; r < rCount; r++) {

1806 FloatReg srcReg1 = srcRegs1[r];

1806 float srcReg1 = srcRegs1[r];

1807 %(destType)s destReg;
1808 %(readDest)s
1809 %(op)s
1810 %(writeDest)s
1811 }
1812 ''' % { "op" : op,
1813 "readDest" : readDestCode,
1814 "destType" : destType,

--- 1738 unchanged lines hidden (view full) ---

3553 twoRegMiscInstFp("vneg", "NVnegDFp", "SimdFloatAluOp", ("float",), 2, vnegfpCode)
3554 twoRegMiscInstFp("vneg", "NVnegQFp", "SimdFloatAluOp", ("float",), 4, vnegfpCode)
3555
3556 vcgtCode = 'destElem = (srcElem1 > 0) ? mask(sizeof(Element) * 8) : 0;'
3557 twoRegMiscInst("vcgt", "NVcgtD", "SimdCmpOp", signedTypes, 2, vcgtCode)
3558 twoRegMiscInst("vcgt", "NVcgtQ", "SimdCmpOp", signedTypes, 4, vcgtCode)
3559 vcgtfpCode = '''
3560 FPSCR fpscr = (FPSCR) FpscrExc;

3561 float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcgtFunc,

3561 float res = binaryOp(fpscr, srcReg1, (float)0.0, vcgtFunc,

3562 true, true, VfpRoundNearest);
3563 destReg = (res == 0) ? -1 : 0;
3564 if (res == 2.0)
3565 fpscr.ioc = 1;
3566 FpscrExc = fpscr;
3567 '''
3568 twoRegMiscInstFp("vcgt", "NVcgtDFp", "SimdFloatCmpOp", ("float",),
3569 2, vcgtfpCode, toInt = True)
3570 twoRegMiscInstFp("vcgt", "NVcgtQFp", "SimdFloatCmpOp", ("float",),
3571 4, vcgtfpCode, toInt = True)
3572
3573 vcgeCode = 'destElem = (srcElem1 >= 0) ? mask(sizeof(Element) * 8) : 0;'
3574 twoRegMiscInst("vcge", "NVcgeD", "SimdCmpOp", signedTypes, 2, vcgeCode)
3575 twoRegMiscInst("vcge", "NVcgeQ", "SimdCmpOp", signedTypes, 4, vcgeCode)
3576 vcgefpCode = '''
3577 FPSCR fpscr = (FPSCR) FpscrExc;

3578 float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcgeFunc,

3578 float res = binaryOp(fpscr, srcReg1, (float)0.0, vcgeFunc,

3579 true, true, VfpRoundNearest);
3580 destReg = (res == 0) ? -1 : 0;
3581 if (res == 2.0)
3582 fpscr.ioc = 1;
3583 FpscrExc = fpscr;
3584 '''
3585 twoRegMiscInstFp("vcge", "NVcgeDFp", "SimdFloatCmpOp", ("float",),
3586 2, vcgefpCode, toInt = True)
3587 twoRegMiscInstFp("vcge", "NVcgeQFp", "SimdFloatCmpOp", ("float",),
3588 4, vcgefpCode, toInt = True)
3589
3590 vceqCode = 'destElem = (srcElem1 == 0) ? mask(sizeof(Element) * 8) : 0;'
3591 twoRegMiscInst("vceq", "NVceqD", "SimdCmpOp", signedTypes, 2, vceqCode)
3592 twoRegMiscInst("vceq", "NVceqQ", "SimdCmpOp", signedTypes, 4, vceqCode)
3593 vceqfpCode = '''
3594 FPSCR fpscr = (FPSCR) FpscrExc;

3595 float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vceqFunc,

3595 float res = binaryOp(fpscr, srcReg1, (float)0.0, vceqFunc,

3596 true, true, VfpRoundNearest);
3597 destReg = (res == 0) ? -1 : 0;
3598 if (res == 2.0)
3599 fpscr.ioc = 1;
3600 FpscrExc = fpscr;
3601 '''
3602 twoRegMiscInstFp("vceq", "NVceqDFp", "SimdFloatCmpOp", ("float",),
3603 2, vceqfpCode, toInt = True)
3604 twoRegMiscInstFp("vceq", "NVceqQFp", "SimdFloatCmpOp", ("float",),
3605 4, vceqfpCode, toInt = True)
3606
3607 vcleCode = 'destElem = (srcElem1 <= 0) ? mask(sizeof(Element) * 8) : 0;'
3608 twoRegMiscInst("vcle", "NVcleD", "SimdCmpOp", signedTypes, 2, vcleCode)
3609 twoRegMiscInst("vcle", "NVcleQ", "SimdCmpOp", signedTypes, 4, vcleCode)
3610 vclefpCode = '''
3611 FPSCR fpscr = (FPSCR) FpscrExc;

3612 float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcleFunc,

3612 float res = binaryOp(fpscr, srcReg1, (float)0.0, vcleFunc,

3613 true, true, VfpRoundNearest);
3614 destReg = (res == 0) ? -1 : 0;
3615 if (res == 2.0)
3616 fpscr.ioc = 1;
3617 FpscrExc = fpscr;
3618 '''
3619 twoRegMiscInstFp("vcle", "NVcleDFp", "SimdFloatCmpOp", ("float",),
3620 2, vclefpCode, toInt = True)
3621 twoRegMiscInstFp("vcle", "NVcleQFp", "SimdFloatCmpOp", ("float",),
3622 4, vclefpCode, toInt = True)
3623
3624 vcltCode = 'destElem = (srcElem1 < 0) ? mask(sizeof(Element) * 8) : 0;'
3625 twoRegMiscInst("vclt", "NVcltD", "SimdCmpOp", signedTypes, 2, vcltCode)
3626 twoRegMiscInst("vclt", "NVcltQ", "SimdCmpOp", signedTypes, 4, vcltCode)
3627 vcltfpCode = '''
3628 FPSCR fpscr = (FPSCR) FpscrExc;

3629 float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcltFunc,

3629 float res = binaryOp(fpscr, srcReg1, (float)0.0, vcltFunc,

3630 true, true, VfpRoundNearest);
3631 destReg = (res == 0) ? -1 : 0;
3632 if (res == 2.0)
3633 fpscr.ioc = 1;
3634 FpscrExc = fpscr;
3635 '''
3636 twoRegMiscInstFp("vclt", "NVcltDFp", "SimdFloatCmpOp", ("float",),
3637 2, vcltfpCode, toInt = True)
3638 twoRegMiscInstFp("vclt", "NVcltQFp", "SimdFloatCmpOp", ("float",),
3639 4, vcltfpCode, toInt = True)
3640
3641 vswpCode = '''

3642 FloatRegBits mid;

3642 uint32_t mid;

3643 for (unsigned r = 0; r < rCount; r++) {
3644 mid = srcReg1.regs[r];
3645 srcReg1.regs[r] = destReg.regs[r];
3646 destReg.regs[r] = mid;
3647 }
3648 '''
3649 twoRegMiscScramble("vswp", "NVswpD", "SimdAluOp", ("uint64_t",), 2, vswpCode)
3650 twoRegMiscScramble("vswp", "NVswpQ", "SimdAluOp", ("uint64_t",), 4, vswpCode)

--- 180 unchanged lines hidden (view full) ---

3831 buildVext("vext", "NVextQ", "SimdMiscOp", ("uint8_t",), 4, vextCode)
3832
3833 def buildVtbxl(name, Name, opClass, length, isVtbl):
3834 global header_output, decoder_output, exec_output
3835 code = simdEnabledCheckCode + '''
3836 union
3837 {
3838 uint8_t bytes[32];

3839 FloatRegBits regs[8];

3839 uint32_t regs[8];

3840 } table;
3841
3842 union
3843 {
3844 uint8_t bytes[8];

3845 FloatRegBits regs[2];

3845 uint32_t regs[2];