neon.isa (10829:1e38e545823b) neon.isa (11443:df24b9af42c7)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2015 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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2934 } else {
2935 destElem += srcElem1;
2936 }
2937 '''
2938 twoRegShiftInst("vrsra", "NVrsraD", "SimdShiftAccOp", allTypes, 2, vrsraCode, True)
2939 twoRegShiftInst("vrsra", "NVrsraQ", "SimdShiftAccOp", allTypes, 4, vrsraCode, True)
2940
2941 vsriCode = '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2015 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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2934 } else {
2935 destElem += srcElem1;
2936 }
2937 '''
2938 twoRegShiftInst("vrsra", "NVrsraD", "SimdShiftAccOp", allTypes, 2, vrsraCode, True)
2939 twoRegShiftInst("vrsra", "NVrsraQ", "SimdShiftAccOp", allTypes, 4, vrsraCode, True)
2940
2941 vsriCode = '''
2942 if (imm >= sizeof(Element) * 8)
2942 if (imm >= sizeof(Element) * 8) {
2943 destElem = destElem;
2943 destElem = destElem;
2944 else
2944 } else {
2945 destElem = (srcElem1 >> imm) |
2946 (destElem & ~mask(sizeof(Element) * 8 - imm));
2945 destElem = (srcElem1 >> imm) |
2946 (destElem & ~mask(sizeof(Element) * 8 - imm));
2947 }
2947 '''
2948 twoRegShiftInst("vsri", "NVsriD", "SimdShiftOp", unsignedTypes, 2, vsriCode, True)
2949 twoRegShiftInst("vsri", "NVsriQ", "SimdShiftOp", unsignedTypes, 4, vsriCode, True)
2950
2951 vshlCode = '''
2948 '''
2949 twoRegShiftInst("vsri", "NVsriD", "SimdShiftOp", unsignedTypes, 2, vsriCode, True)
2950 twoRegShiftInst("vsri", "NVsriQ", "SimdShiftOp", unsignedTypes, 4, vsriCode, True)
2951
2952 vshlCode = '''
2952 if (imm >= sizeof(Element) * 8)
2953 if (imm >= sizeof(Element) * 8) {
2953 destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1;
2954 destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1;
2954 else
2955 } else {
2955 destElem = srcElem1 << imm;
2956 destElem = srcElem1 << imm;
2957 }
2956 '''
2957 twoRegShiftInst("vshl", "NVshlD", "SimdShiftOp", unsignedTypes, 2, vshlCode)
2958 twoRegShiftInst("vshl", "NVshlQ", "SimdShiftOp", unsignedTypes, 4, vshlCode)
2959
2960 vsliCode = '''
2958 '''
2959 twoRegShiftInst("vshl", "NVshlD", "SimdShiftOp", unsignedTypes, 2, vshlCode)
2960 twoRegShiftInst("vshl", "NVshlQ", "SimdShiftOp", unsignedTypes, 4, vshlCode)
2961
2962 vsliCode = '''
2961 if (imm >= sizeof(Element) * 8)
2963 if (imm >= sizeof(Element) * 8) {
2962 destElem = destElem;
2964 destElem = destElem;
2963 else
2965 } else {
2964 destElem = (srcElem1 << imm) | (destElem & mask(imm));
2966 destElem = (srcElem1 << imm) | (destElem & mask(imm));
2967 }
2965 '''
2966 twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2, vsliCode, True)
2967 twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4, vsliCode, True)
2968
2969 vqshlCode = '''
2970 FPSCR fpscr = (FPSCR) FpscrQc;
2971 if (imm >= sizeof(Element) * 8) {
2972 if (srcElem1 != 0) {

--- 917 unchanged lines hidden --- 		2968 '''
2969 twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2, vsliCode, True)
2970 twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4, vsliCode, True)
2971
2972 vqshlCode = '''
2973 FPSCR fpscr = (FPSCR) FpscrQc;
2974 if (imm >= sizeof(Element) * 8) {
2975 if (srcElem1 != 0) {

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