1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 1704 unchanged lines hidden (view full) --- 1713 shiftAmt = -shiftAmt; 1714 if (shiftAmt >= sizeof(Element) * 8) { 1715 shiftAmt = sizeof(Element) * 8 - 1; 1716 destElem = 0; 1717 } else { 1718 destElem = (srcElem1 >> shiftAmt); 1719 } 1720 // Make sure the right shift sign extended when it should. |
1721 if (ltz(srcElem1) && !ltz(destElem)) { |
1722 destElem |= -((Element)1 << (sizeof(Element) * 8 - 1723 1 - shiftAmt)); 1724 } 1725 } else { 1726 if (shiftAmt >= sizeof(Element) * 8) { 1727 destElem = 0; 1728 } else { 1729 destElem = srcElem1 << shiftAmt; --- 5 unchanged lines hidden (view full) --- 1735 1736 vrshlCode = ''' 1737 int16_t shiftAmt = (int8_t)srcElem2; 1738 if (shiftAmt < 0) { 1739 shiftAmt = -shiftAmt; 1740 Element rBit = 0; 1741 if (shiftAmt <= sizeof(Element) * 8) 1742 rBit = bits(srcElem1, shiftAmt - 1); |
1743 if (shiftAmt > sizeof(Element) * 8 && ltz(srcElem1)) |
1744 rBit = 1; 1745 if (shiftAmt >= sizeof(Element) * 8) { 1746 shiftAmt = sizeof(Element) * 8 - 1; 1747 destElem = 0; 1748 } else { 1749 destElem = (srcElem1 >> shiftAmt); 1750 } 1751 // Make sure the right shift sign extended when it should. |
1752 if (ltz(srcElem1) && !ltz(destElem)) { |
1753 destElem |= -((Element)1 << (sizeof(Element) * 8 - 1754 1 - shiftAmt)); 1755 } 1756 destElem += rBit; 1757 } else if (shiftAmt > 0) { 1758 if (shiftAmt >= sizeof(Element) * 8) { 1759 destElem = 0; 1760 } else { --- 12 unchanged lines hidden (view full) --- 1773 if (shiftAmt < 0) { 1774 shiftAmt = -shiftAmt; 1775 if (shiftAmt >= sizeof(Element) * 8) { 1776 shiftAmt = sizeof(Element) * 8 - 1; 1777 destElem = 0; 1778 } else { 1779 destElem = (srcElem1 >> shiftAmt); 1780 } |
1781 } else if (shiftAmt > 0) { 1782 if (shiftAmt >= sizeof(Element) * 8) { 1783 if (srcElem1 != 0) { 1784 destElem = mask(sizeof(Element) * 8); 1785 fpscr.qc = 1; 1786 } else { 1787 destElem = 0; 1788 } --- 63 unchanged lines hidden (view full) --- 1852 vqrshlUCode = ''' 1853 int16_t shiftAmt = (int8_t)srcElem2; 1854 FPSCR fpscr = (FPSCR)Fpscr; 1855 if (shiftAmt < 0) { 1856 shiftAmt = -shiftAmt; 1857 Element rBit = 0; 1858 if (shiftAmt <= sizeof(Element) * 8) 1859 rBit = bits(srcElem1, shiftAmt - 1); |
1860 if (shiftAmt >= sizeof(Element) * 8) { 1861 shiftAmt = sizeof(Element) * 8 - 1; 1862 destElem = 0; 1863 } else { 1864 destElem = (srcElem1 >> shiftAmt); 1865 } |
1866 destElem += rBit; 1867 } else { 1868 if (shiftAmt >= sizeof(Element) * 8) { 1869 if (srcElem1 != 0) { 1870 destElem = mask(sizeof(Element) * 8); 1871 fpscr.qc = 1; 1872 } else { 1873 destElem = 0; --- 123 unchanged lines hidden (view full) --- 1997 Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1); 1998 Element halfNeg = maxNeg / 2; 1999 if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 2000 (srcElem1 == halfNeg && srcElem2 == maxNeg) || 2001 (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 2002 midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 2003 fpscr.qc = 1; 2004 } |
2005 bool negPreDest = ltz(destElem); |
2006 destElem += midElem; |
2007 bool negDest = ltz(destElem); 2008 bool negMid = ltz(midElem); |
2009 if (negPreDest == negMid && negMid != negDest) { 2010 destElem = mask(sizeof(BigElement) * 8 - 1); 2011 if (negPreDest) 2012 destElem = ~destElem; 2013 fpscr.qc = 1; 2014 } 2015 Fpscr = fpscr; 2016 ''' --- 5 unchanged lines hidden (view full) --- 2022 Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1); 2023 Element halfNeg = maxNeg / 2; 2024 if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 2025 (srcElem1 == halfNeg && srcElem2 == maxNeg) || 2026 (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 2027 midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 2028 fpscr.qc = 1; 2029 } |
2030 bool negPreDest = ltz(destElem); |
2031 destElem -= midElem; |
2032 bool negDest = ltz(destElem); 2033 bool posMid = ltz((BigElement)-midElem); |
2034 if (negPreDest == posMid && posMid != negDest) { 2035 destElem = mask(sizeof(BigElement) * 8 - 1); 2036 if (negPreDest) 2037 destElem = ~destElem; 2038 fpscr.qc = 1; 2039 } 2040 Fpscr = fpscr; 2041 ''' --- 302 unchanged lines hidden (view full) --- 2344 twoEqualRegInst("vqdmulh", "VqdmulhsQ", smallSignedTypes, 4, vqdmulhCode) 2345 twoEqualRegInst("vqrdmulh", "VqrdmulhsD", 2346 smallSignedTypes, 2, vqrdmulhCode) 2347 twoEqualRegInst("vqrdmulh", "VqrdmulhsQ", 2348 smallSignedTypes, 4, vqrdmulhCode) 2349 2350 vshrCode = ''' 2351 if (imm >= sizeof(srcElem1) * 8) { |
2352 if (ltz(srcElem1)) |
2353 destElem = -1; 2354 else 2355 destElem = 0; 2356 } else { 2357 destElem = srcElem1 >> imm; 2358 } 2359 ''' 2360 twoRegShiftInst("vshr", "NVshrD", allTypes, 2, vshrCode) 2361 twoRegShiftInst("vshr", "NVshrQ", allTypes, 4, vshrCode) 2362 2363 vsraCode = ''' 2364 Element mid;; 2365 if (imm >= sizeof(srcElem1) * 8) { |
2366 mid = ltz(srcElem1) ? -1 : 0; |
2367 } else { 2368 mid = srcElem1 >> imm; |
2369 if (ltz(srcElem1) && !ltz(mid)) { |
2370 mid |= -(mid & ((Element)1 << 2371 (sizeof(Element) * 8 - 1 - imm))); 2372 } 2373 } 2374 destElem += mid; 2375 ''' 2376 twoRegShiftInst("vsra", "NVsraD", allTypes, 2, vsraCode, True) 2377 twoRegShiftInst("vsra", "NVsraQ", allTypes, 4, vsraCode, True) --- 291 unchanged lines hidden (view full) --- 2669 destElem = mask(sizeof(Element) * 8); 2670 fpscr.qc = 1; 2671 } else { 2672 destElem = mid; 2673 } 2674 } else { 2675 if (srcElem1 != (Element)srcElem1) { 2676 destElem = mask(sizeof(Element) * 8 - 1); |
2677 fpscr.qc = 1; 2678 } else { 2679 destElem = srcElem1; 2680 } 2681 } 2682 Fpscr = fpscr; 2683 ''' 2684 twoRegNarrowShiftInst("vqrshrun", "NVqrshrun", --- 652 unchanged lines hidden --- |