1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2011, 2015 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 2156 unchanged lines hidden (view full) --- 2165 2166 vqaddSCode = ''' 2167 destElem = srcElem1 + srcElem2; 2168 FPSCR fpscr = (FPSCR) FpscrQc; 2169 bool negDest = (destElem < 0); 2170 bool negSrc1 = (srcElem1 < 0); 2171 bool negSrc2 = (srcElem2 < 0); 2172 if ((negDest != negSrc1) && (negSrc1 == negSrc2)) { |
2173 if (negDest) |
2174 /* If (>=0) plus (>=0) yields (<0), saturate to +. */ 2175 destElem = std::numeric_limits<Element>::max(); 2176 else 2177 /* If (<0) plus (<0) yields (>=0), saturate to -. */ 2178 destElem = std::numeric_limits<Element>::min(); |
2179 fpscr.qc = 1; 2180 } 2181 FpscrQc = fpscr; 2182 ''' 2183 threeEqualRegInst("vqadd", "VqaddSD", "SimdAddOp", signedTypes, 2, vqaddSCode) 2184 threeEqualRegInst("vqadd", "VqaddSQ", "SimdAddOp", signedTypes, 4, vqaddSCode) 2185 2186 vqsubUCode = ''' --- 10 unchanged lines hidden (view full) --- 2197 2198 vqsubSCode = ''' 2199 destElem = srcElem1 - srcElem2; 2200 FPSCR fpscr = (FPSCR) FpscrQc; 2201 bool negDest = (destElem < 0); 2202 bool negSrc1 = (srcElem1 < 0); 2203 bool posSrc2 = (srcElem2 >= 0); 2204 if ((negDest != negSrc1) && (negSrc1 == posSrc2)) { |
2205 if (negDest) |
2206 /* If (>=0) minus (<0) yields (<0), saturate to +. */ 2207 destElem = std::numeric_limits<Element>::max(); 2208 else 2209 /* If (<0) minus (>=0) yields (>=0), saturate to -. */ 2210 destElem = std::numeric_limits<Element>::min(); |
2211 fpscr.qc = 1; 2212 } 2213 FpscrQc = fpscr; 2214 ''' 2215 threeEqualRegInst("vqsub", "VqsubSD", "SimdAddOp", signedTypes, 2, vqsubSCode) 2216 threeEqualRegInst("vqsub", "VqsubSQ", "SimdAddOp", signedTypes, 4, vqsubSCode) 2217 2218 vcgtCode = ''' --- 296 unchanged lines hidden (view full) --- 2515 vmlalCode = ''' 2516 destElem = destElem + (BigElement)srcElem1 * (BigElement)srcElem2; 2517 ''' 2518 threeRegLongInst("vmlal", "Vmlal", "SimdMultAccOp", smallTypes, vmlalCode, True) 2519 2520 vqdmlalCode = ''' 2521 FPSCR fpscr = (FPSCR) FpscrQc; 2522 BigElement midElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); |
2523 Element maxNeg = std::numeric_limits<Element>::min(); |
2524 Element halfNeg = maxNeg / 2; 2525 if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 2526 (srcElem1 == halfNeg && srcElem2 == maxNeg) || 2527 (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 2528 midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 2529 fpscr.qc = 1; 2530 } 2531 bool negPreDest = ltz(destElem); --- 8 unchanged lines hidden (view full) --- 2540 } 2541 FpscrQc = fpscr; 2542 ''' 2543 threeRegLongInst("vqdmlal", "Vqdmlal", "SimdMultAccOp", smallTypes, vqdmlalCode, True) 2544 2545 vqdmlslCode = ''' 2546 FPSCR fpscr = (FPSCR) FpscrQc; 2547 BigElement midElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); |
2548 Element maxNeg = std::numeric_limits<Element>::min(); |
2549 Element halfNeg = maxNeg / 2; 2550 if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 2551 (srcElem1 == halfNeg && srcElem2 == maxNeg) || 2552 (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 2553 midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 2554 fpscr.qc = 1; 2555 } 2556 bool negPreDest = ltz(destElem); --- 9 unchanged lines hidden (view full) --- 2566 FpscrQc = fpscr; 2567 ''' 2568 threeRegLongInst("vqdmlsl", "Vqdmlsl", "SimdMultAccOp", smallTypes, vqdmlslCode, True) 2569 2570 vqdmullCode = ''' 2571 FPSCR fpscr = (FPSCR) FpscrQc; 2572 destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 2573 if (srcElem1 == srcElem2 && |
2574 srcElem1 == (Element)(std::numeric_limits<Element>::min())) { |
2575 destElem = ~((BigElement)srcElem1 << (sizeof(Element) * 8)); 2576 fpscr.qc = 1; 2577 } 2578 FpscrQc = fpscr; 2579 ''' 2580 threeRegLongInst("vqdmull", "Vqdmull", "SimdMultAccOp", smallTypes, vqdmullCode) 2581 2582 vmlsCode = ''' --- 28 unchanged lines hidden (view full) --- 2611 2612 threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True) 2613 2614 vqdmulhCode = ''' 2615 FPSCR fpscr = (FPSCR) FpscrQc; 2616 destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2) >> 2617 (sizeof(Element) * 8); 2618 if (srcElem1 == srcElem2 && |
2619 srcElem1 == (Element)(std::numeric_limits<Element>::min())) { |
2620 destElem = ~srcElem1; 2621 fpscr.qc = 1; 2622 } 2623 FpscrQc = fpscr; 2624 ''' 2625 threeEqualRegInst("vqdmulh", "VqdmulhD", "SimdMultOp", smallSignedTypes, 2, vqdmulhCode) 2626 threeEqualRegInst("vqdmulh", "VqdmulhQ", "SimdMultOp", smallSignedTypes, 4, vqdmulhCode) 2627 2628 vqrdmulhCode = ''' 2629 FPSCR fpscr = (FPSCR) FpscrQc; 2630 destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2 + 2631 ((int64_t)1 << (sizeof(Element) * 8 - 1))) >> 2632 (sizeof(Element) * 8); |
2633 Element maxNeg = std::numeric_limits<Element>::min(); |
2634 Element halfNeg = maxNeg / 2; 2635 if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 2636 (srcElem1 == halfNeg && srcElem2 == maxNeg) || 2637 (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 2638 if (destElem < 0) { 2639 destElem = mask(sizeof(Element) * 8 - 1); 2640 } else { |
2641 destElem = std::numeric_limits<Element>::min(); |
2642 } 2643 fpscr.qc = 1; 2644 } 2645 FpscrQc = fpscr; 2646 ''' 2647 threeEqualRegInst("vqrdmulh", "VqrdmulhD", 2648 "SimdMultOp", smallSignedTypes, 2, vqrdmulhCode) 2649 threeEqualRegInst("vqrdmulh", "VqrdmulhQ", --- 322 unchanged lines hidden (view full) --- 2972 ''' 2973 twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2, vsliCode, True) 2974 twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4, vsliCode, True) 2975 2976 vqshlCode = ''' 2977 FPSCR fpscr = (FPSCR) FpscrQc; 2978 if (imm >= sizeof(Element) * 8) { 2979 if (srcElem1 != 0) { |
2980 destElem = std::numeric_limits<Element>::min(); |
2981 if (srcElem1 > 0) 2982 destElem = ~destElem; 2983 fpscr.qc = 1; 2984 } else { 2985 destElem = 0; 2986 } 2987 } else if (imm) { 2988 destElem = (srcElem1 << imm); 2989 uint64_t topBits = bits((uint64_t)srcElem1, 2990 sizeof(Element) * 8 - 1, 2991 sizeof(Element) * 8 - 1 - imm); 2992 if (topBits != 0 && topBits != mask(imm + 1)) { |
2993 destElem = std::numeric_limits<Element>::min(); |
2994 if (srcElem1 > 0) 2995 destElem = ~destElem; 2996 fpscr.qc = 1; 2997 } 2998 } else { 2999 destElem = srcElem1; 3000 } 3001 FpscrQc = fpscr; --- 486 unchanged lines hidden (view full) --- 3488 vmvnCode = ''' 3489 destElem = ~srcElem1; 3490 ''' 3491 twoRegMiscInst("vmvn", "NVmvnD", "SimdAluOp", ("uint64_t",), 2, vmvnCode) 3492 twoRegMiscInst("vmvn", "NVmvnQ", "SimdAluOp", ("uint64_t",), 4, vmvnCode) 3493 3494 vqabsCode = ''' 3495 FPSCR fpscr = (FPSCR) FpscrQc; |
3496 if (srcElem1 == (Element)(std::numeric_limits<Element>::min())) { |
3497 fpscr.qc = 1; 3498 destElem = ~srcElem1; 3499 } else if (srcElem1 < 0) { 3500 destElem = -srcElem1; 3501 } else { 3502 destElem = srcElem1; 3503 } 3504 FpscrQc = fpscr; 3505 ''' 3506 twoRegMiscInst("vqabs", "NVqabsD", "SimdAluOp", signedTypes, 2, vqabsCode) 3507 twoRegMiscInst("vqabs", "NVqabsQ", "SimdAluOp", signedTypes, 4, vqabsCode) 3508 3509 vqnegCode = ''' 3510 FPSCR fpscr = (FPSCR) FpscrQc; |
3511 if (srcElem1 == (Element)(std::numeric_limits<Element>::min())) { |
3512 fpscr.qc = 1; 3513 destElem = ~srcElem1; 3514 } else { 3515 destElem = -srcElem1; 3516 } 3517 FpscrQc = fpscr; 3518 ''' 3519 twoRegMiscInst("vqneg", "NVqnegD", "SimdAluOp", signedTypes, 2, vqnegCode) --- 377 unchanged lines hidden --- |