1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2011 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 1044 unchanged lines hidden (view full) --- 1053 return new BaseD<int16_t>(machInst, dest, op1); 1054 default: 1055 return new Unknown(machInst); 1056 } 1057 } 1058 } 1059}}; 1060 |
1061let {{ 1062 header_output = "" 1063 exec_output = "" 1064 1065 vcompares = ''' |
1066 static float 1067 vcgtFunc(float op1, float op2) 1068 { 1069 if (std::isnan(op1) || std::isnan(op2)) 1070 return 2.0; 1071 return (op1 > op2) ? 0.0 : 1.0; 1072 } 1073 --- 7 unchanged lines hidden (view full) --- 1081 1082 static float 1083 vceqFunc(float op1, float op2) 1084 { 1085 if (isSnan(op1) || isSnan(op2)) 1086 return 2.0; 1087 return (op1 == op2) ? 0.0 : 1.0; 1088 } |
1089''' 1090 vcomparesL = ''' |
1091 static float 1092 vcleFunc(float op1, float op2) 1093 { 1094 if (std::isnan(op1) || std::isnan(op2)) 1095 return 2.0; 1096 return (op1 <= op2) ? 0.0 : 1.0; 1097 } 1098 1099 static float 1100 vcltFunc(float op1, float op2) 1101 { 1102 if (std::isnan(op1) || std::isnan(op2)) 1103 return 2.0; 1104 return (op1 < op2) ? 0.0 : 1.0; 1105 } |
1106''' 1107 vacomparesG = ''' |
1108 static float 1109 vacgtFunc(float op1, float op2) 1110 { 1111 if (std::isnan(op1) || std::isnan(op2)) 1112 return 2.0; 1113 return (fabsf(op1) > fabsf(op2)) ? 0.0 : 1.0; 1114 } 1115 1116 static float 1117 vacgeFunc(float op1, float op2) 1118 { 1119 if (std::isnan(op1) || std::isnan(op2)) 1120 return 2.0; 1121 return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0; 1122 } |
1123''' |
1124 |
1125 exec_output += vcompares + vacomparesG |
1126 |
1127 smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t") 1128 unsignedTypes = smallUnsignedTypes + ("uint64_t",) 1129 smallSignedTypes = ("int8_t", "int16_t", "int32_t") 1130 signedTypes = smallSignedTypes + ("int64_t",) 1131 smallTypes = smallUnsignedTypes + smallSignedTypes 1132 allTypes = unsignedTypes + signedTypes 1133 1134 def threeEqualRegInst(name, Name, opClass, types, rCount, op, --- 2277 unchanged lines hidden (view full) --- 3412 destElem = srcElem1; 3413 unsigned groupSize = ((1 << 3) / sizeof(Element)); 3414 unsigned reverseMask = (groupSize - 1); 3415 j = i ^ reverseMask; 3416 ''' 3417 twoRegMiscInst("vrev64", "NVrev64D", "SimdAluOp", smallUnsignedTypes, 2, vrev64Code) 3418 twoRegMiscInst("vrev64", "NVrev64Q", "SimdAluOp", smallUnsignedTypes, 4, vrev64Code) 3419 |
3420 split('exec') 3421 exec_output += vcompares + vcomparesL 3422 |
3423 vpaddlCode = ''' 3424 destElem = (BigElement)srcElem1 + (BigElement)srcElem2; 3425 ''' 3426 twoRegCondenseInst("vpaddl", "NVpaddlD", "SimdAddOp", smallTypes, 2, vpaddlCode) 3427 twoRegCondenseInst("vpaddl", "NVpaddlQ", "SimdAddOp", smallTypes, 4, vpaddlCode) 3428 3429 vpadalCode = ''' 3430 destElem += (BigElement)srcElem1 + (BigElement)srcElem2; --- 454 unchanged lines hidden --- |