1622c1622
< threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes,
---
> threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes,
1624,1625d1623
< threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes,
< 4, vaddCode, pairwise=True)
2116,2117c2114
< threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True)
< threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True)
---
> threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True)
2119,2120c2116
< threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True)
< threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True)
---
> threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True)
3143,3144c3139,3142
< twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode)
< twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode)
---
> twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp",
> smallUnsignedTypes, 2, vtrnCode)
> twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp",
> smallUnsignedTypes, 4, vtrnCode)