1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1713 shiftAmt = -shiftAmt;
1714 if (shiftAmt >= sizeof(Element) * 8) {
1715 shiftAmt = sizeof(Element) * 8 - 1;
1716 destElem = 0;
1717 } else {
1718 destElem = (srcElem1 >> shiftAmt);
1719 }
1720 // Make sure the right shift sign extended when it should.
1721 if (srcElem1 < 0 && destElem >= 0) {
1722 destElem |= -((Element)1 << (sizeof(Element) * 8 -
1723 1 - shiftAmt));
1724 }
1725 } else {
1726 if (shiftAmt >= sizeof(Element) * 8) {
1727 destElem = 0;
1728 } else {
1729 destElem = srcElem1 << shiftAmt;

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1735
1736 vrshlCode = '''
1737 int16_t shiftAmt = (int8_t)srcElem2;
1738 if (shiftAmt < 0) {
1739 shiftAmt = -shiftAmt;
1740 Element rBit = 0;
1741 if (shiftAmt <= sizeof(Element) * 8)
1742 rBit = bits(srcElem1, shiftAmt - 1);
1743 if (shiftAmt > sizeof(Element) * 8 && srcElem1 < 0)
1744 rBit = 1;
1745 if (shiftAmt >= sizeof(Element) * 8) {
1746 shiftAmt = sizeof(Element) * 8 - 1;
1747 destElem = 0;
1748 } else {
1749 destElem = (srcElem1 >> shiftAmt);
1750 }
1751 // Make sure the right shift sign extended when it should.
1752 if (srcElem1 < 0 && destElem >= 0) {
1753 destElem |= -((Element)1 << (sizeof(Element) * 8 -
1754 1 - shiftAmt));
1755 }
1756 destElem += rBit;
1757 } else if (shiftAmt > 0) {
1758 if (shiftAmt >= sizeof(Element) * 8) {
1759 destElem = 0;
1760 } else {

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1773 if (shiftAmt < 0) {
1774 shiftAmt = -shiftAmt;
1775 if (shiftAmt >= sizeof(Element) * 8) {
1776 shiftAmt = sizeof(Element) * 8 - 1;
1777 destElem = 0;
1778 } else {
1779 destElem = (srcElem1 >> shiftAmt);
1780 }
1781 // Make sure the right shift sign extended when it should.
1782 if (srcElem1 < 0 && destElem >= 0) {
1783 destElem |= -((Element)1 << (sizeof(Element) * 8 -
1784 1 - shiftAmt));
1785 }
1786 } else if (shiftAmt > 0) {
1787 if (shiftAmt >= sizeof(Element) * 8) {
1788 if (srcElem1 != 0) {
1789 destElem = mask(sizeof(Element) * 8);
1790 fpscr.qc = 1;
1791 } else {
1792 destElem = 0;
1793 }

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1857 vqrshlUCode = '''
1858 int16_t shiftAmt = (int8_t)srcElem2;
1859 FPSCR fpscr = (FPSCR)Fpscr;
1860 if (shiftAmt < 0) {
1861 shiftAmt = -shiftAmt;
1862 Element rBit = 0;
1863 if (shiftAmt <= sizeof(Element) * 8)
1864 rBit = bits(srcElem1, shiftAmt - 1);
1865 if (shiftAmt > sizeof(Element) * 8 && srcElem1 < 0)
1866 rBit = 1;
1867 if (shiftAmt >= sizeof(Element) * 8) {
1868 shiftAmt = sizeof(Element) * 8 - 1;
1869 destElem = 0;
1870 } else {
1871 destElem = (srcElem1 >> shiftAmt);
1872 }
1873 // Make sure the right shift sign extended when it should.
1874 if (srcElem1 < 0 && destElem >= 0) {
1875 destElem |= -((Element)1 << (sizeof(Element) * 8 -
1876 1 - shiftAmt));
1877 }
1878 destElem += rBit;
1879 } else {
1880 if (shiftAmt >= sizeof(Element) * 8) {
1881 if (srcElem1 != 0) {
1882 destElem = mask(sizeof(Element) * 8);
1883 fpscr.qc = 1;
1884 } else {
1885 destElem = 0;

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2009 Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1);
2010 Element halfNeg = maxNeg / 2;
2011 if ((srcElem1 == maxNeg && srcElem2 == maxNeg) ||
2012 (srcElem1 == halfNeg && srcElem2 == maxNeg) ||
2013 (srcElem1 == maxNeg && srcElem2 == halfNeg)) {
2014 midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8));
2015 fpscr.qc = 1;
2016 }
2017 bool negPreDest = (destElem < 0);
2018 destElem += midElem;
2019 bool negDest = (destElem < 0);
2020 bool negMid = (midElem < 0);
2021 if (negPreDest == negMid && negMid != negDest) {
2022 destElem = mask(sizeof(BigElement) * 8 - 1);
2023 if (negPreDest)
2024 destElem = ~destElem;
2025 fpscr.qc = 1;
2026 }
2027 Fpscr = fpscr;
2028 '''

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2034 Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1);
2035 Element halfNeg = maxNeg / 2;
2036 if ((srcElem1 == maxNeg && srcElem2 == maxNeg) ||
2037 (srcElem1 == halfNeg && srcElem2 == maxNeg) ||
2038 (srcElem1 == maxNeg && srcElem2 == halfNeg)) {
2039 midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8));
2040 fpscr.qc = 1;
2041 }
2042 bool negPreDest = (destElem < 0);
2043 destElem -= midElem;
2044 bool negDest = (destElem < 0);
2045 bool posMid = (midElem > 0);
2046 if (negPreDest == posMid && posMid != negDest) {
2047 destElem = mask(sizeof(BigElement) * 8 - 1);
2048 if (negPreDest)
2049 destElem = ~destElem;
2050 fpscr.qc = 1;
2051 }
2052 Fpscr = fpscr;
2053 '''

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2356 twoEqualRegInst("vqdmulh", "VqdmulhsQ", smallSignedTypes, 4, vqdmulhCode)
2357 twoEqualRegInst("vqrdmulh", "VqrdmulhsD",
2358 smallSignedTypes, 2, vqrdmulhCode)
2359 twoEqualRegInst("vqrdmulh", "VqrdmulhsQ",
2360 smallSignedTypes, 4, vqrdmulhCode)
2361
2362 vshrCode = '''
2363 if (imm >= sizeof(srcElem1) * 8) {
2364 if (srcElem1 < 0)
2365 destElem = -1;
2366 else
2367 destElem = 0;
2368 } else {
2369 destElem = srcElem1 >> imm;
2370 }
2371 '''
2372 twoRegShiftInst("vshr", "NVshrD", allTypes, 2, vshrCode)
2373 twoRegShiftInst("vshr", "NVshrQ", allTypes, 4, vshrCode)
2374
2375 vsraCode = '''
2376 Element mid;;
2377 if (imm >= sizeof(srcElem1) * 8) {
2378 mid = (srcElem1 < 0) ? -1 : 0;
2379 } else {
2380 mid = srcElem1 >> imm;
2381 if (srcElem1 < 0 && mid >= 0) {
2382 mid |= -(mid & ((Element)1 <<
2383 (sizeof(Element) * 8 - 1 - imm)));
2384 }
2385 }
2386 destElem += mid;
2387 '''
2388 twoRegShiftInst("vsra", "NVsraD", allTypes, 2, vsraCode, True)
2389 twoRegShiftInst("vsra", "NVsraQ", allTypes, 4, vsraCode, True)

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2681 destElem = mask(sizeof(Element) * 8);
2682 fpscr.qc = 1;
2683 } else {
2684 destElem = mid;
2685 }
2686 } else {
2687 if (srcElem1 != (Element)srcElem1) {
2688 destElem = mask(sizeof(Element) * 8 - 1);
2689 if (srcElem1 < 0)
2690 destElem = ~destElem;
2691 fpscr.qc = 1;
2692 } else {
2693 destElem = srcElem1;
2694 }
2695 }
2696 Fpscr = fpscr;
2697 '''
2698 twoRegNarrowShiftInst("vqrshrun", "NVqrshrun",

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