mult.isa (7228:09302e193402) mult.isa (7229:ed81380fd089)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 270 unchanged lines hidden (view full) ---

279 sext<16>(bits(Reg3, 15, 0)) +
280 (int64_t)((Reg1.ud << 32) |
281 Reg0.ud);
282 Reg0.ud = (uint32_t)resTemp;
283 Reg1.ud = (uint32_t)(resTemp >> 32);
284 ''')
285 buildMult4InstUnCc("smmla", '''Reg0 = resTemp =
286 ((int64_t)(Reg3.ud << 32) +
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 270 unchanged lines hidden (view full) ---

279 sext<16>(bits(Reg3, 15, 0)) +
280 (int64_t)((Reg1.ud << 32) |
281 Reg0.ud);
282 Reg0.ud = (uint32_t)resTemp;
283 Reg1.ud = (uint32_t)(resTemp >> 32);
284 ''')
285 buildMult4InstUnCc("smmla", '''Reg0 = resTemp =
286 ((int64_t)(Reg3.ud << 32) +
287 Reg1.sw * Reg2.sw) >> 32;
287 (int64_t)Reg1.sw *
288 (int64_t)Reg2.sw) >> 32;
288 ''')
289 buildMult4InstUnCc("smmlar", '''Reg0 = resTemp =
290 ((int64_t)(Reg3.ud << 32) +
289 ''')
290 buildMult4InstUnCc("smmlar", '''Reg0 = resTemp =
291 ((int64_t)(Reg3.ud << 32) +
291 Reg1.sw * Reg2.sw +
292 (int64_t)Reg1.sw *
293 (int64_t)Reg2.sw +
292 ULL(0x80000000)) >> 32;
293 ''')
294 buildMult4InstUnCc("smmls", '''Reg0 = resTemp =
295 ((int64_t)(Reg3.ud << 32) -
294 ULL(0x80000000)) >> 32;
295 ''')
296 buildMult4InstUnCc("smmls", '''Reg0 = resTemp =
297 ((int64_t)(Reg3.ud << 32) -
296 Reg1.sw * Reg2.sw) >> 32;
298 (int64_t)Reg1.sw *
299 (int64_t)Reg2.sw) >> 32;
297 ''')
298 buildMult4InstUnCc("smmlsr", '''Reg0 = resTemp =
299 ((int64_t)(Reg3.ud << 32) -
300 ''')
301 buildMult4InstUnCc("smmlsr", '''Reg0 = resTemp =
302 ((int64_t)(Reg3.ud << 32) -
300 Reg1.sw * Reg2.sw +
303 (int64_t)Reg1.sw *
304 (int64_t)Reg2.sw +
301 ULL(0x80000000)) >> 32;
302 ''')
303 buildMult3InstUnCc("smmul", '''Reg0 = resTemp =
305 ULL(0x80000000)) >> 32;
306 ''')
307 buildMult3InstUnCc("smmul", '''Reg0 = resTemp =
304 ((int64_t)Reg1 *
305 (int64_t)Reg2) >> 32;
308 ((int64_t)Reg1.sw *
309 (int64_t)Reg2.sw) >> 32;
306 ''')
307 buildMult3InstUnCc("smmulr", '''Reg0 = resTemp =
310 ''')
311 buildMult3InstUnCc("smmulr", '''Reg0 = resTemp =
308 ((int64_t)Reg1 *
309 (int64_t)Reg2 +
312 ((int64_t)Reg1.sw *
313 (int64_t)Reg2.sw +
310 ULL(0x80000000)) >> 32;
311 ''')
312 buildMult3InstCc ("smuad", '''Reg0 = resTemp =
313 sext<16>(bits(Reg1, 15, 0)) *
314 sext<16>(bits(Reg2, 15, 0)) +
315 sext<16>(bits(Reg1, 31, 16)) *
316 sext<16>(bits(Reg2, 31, 16));
317 resTemp = bits(resTemp, 32) !=

--- 66 unchanged lines hidden --- 		314 ULL(0x80000000)) >> 32;
315 ''')
316 buildMult3InstCc ("smuad", '''Reg0 = resTemp =
317 sext<16>(bits(Reg1, 15, 0)) *
318 sext<16>(bits(Reg2, 15, 0)) +
319 sext<16>(bits(Reg1, 31, 16)) *
320 sext<16>(bits(Reg2, 31, 16));
321 resTemp = bits(resTemp, 32) !=

--- 66 unchanged lines hidden ---