1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 151 unchanged lines hidden (view full) --- 160 bits(resTemp, 31); 161 ''', "overflow") 162 buildMult4InstCc ("smlad", '''Reg0 = resTemp = 163 sext<16>(bits(Reg1, 31, 16)) * 164 sext<16>(bits(Reg2, 31, 16)) + 165 sext<16>(bits(Reg1, 15, 0)) * 166 sext<16>(bits(Reg2, 15, 0)) + 167 Reg3.sw; |
168 resTemp = bits(resTemp, 32) != 169 bits(resTemp, 31); |
170 ''', "overflow") 171 buildMult4InstCc ("smladx", '''Reg0 = resTemp = 172 sext<16>(bits(Reg1, 31, 16)) * 173 sext<16>(bits(Reg2, 15, 0)) + 174 sext<16>(bits(Reg1, 15, 0)) * 175 sext<16>(bits(Reg2, 31, 16)) + 176 Reg3.sw; |
177 resTemp = bits(resTemp, 32) != 178 bits(resTemp, 31); |
179 ''', "overflow") 180 buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) + 181 (int64_t)((Reg1.ud << 32) | Reg0.ud); 182 Reg0.ud = (uint32_t)resTemp; 183 Reg1.ud = (uint32_t)(resTemp >> 32); 184 ''', "llbit") 185 buildMult4InstUnCc("smlalbb", '''resTemp = sext<16>(bits(Reg2, 15, 0)) * 186 sext<16>(bits(Reg3, 15, 0)) + --- 58 unchanged lines hidden (view full) --- 245 bits(resTemp, 31); 246 ''', "overflow") 247 buildMult4InstCc ("smlsd", '''Reg0 = resTemp = 248 sext<16>(bits(Reg1, 15, 0)) * 249 sext<16>(bits(Reg2, 15, 0)) - 250 sext<16>(bits(Reg1, 31, 16)) * 251 sext<16>(bits(Reg2, 31, 16)) + 252 Reg3.sw; |
253 resTemp = bits(resTemp, 32) != 254 bits(resTemp, 31); |
255 ''', "overflow") 256 buildMult4InstCc ("smlsdx", '''Reg0 = resTemp = 257 sext<16>(bits(Reg1, 15, 0)) * 258 sext<16>(bits(Reg2, 31, 16)) - 259 sext<16>(bits(Reg1, 31, 16)) * 260 sext<16>(bits(Reg2, 15, 0)) + 261 Reg3.sw; |
262 resTemp = bits(resTemp, 32) != 263 bits(resTemp, 31); |
264 ''', "overflow") 265 buildMult4InstUnCc("smlsld", '''resTemp = 266 sext<16>(bits(Reg2, 15, 0)) * 267 sext<16>(bits(Reg3, 15, 0)) - 268 sext<16>(bits(Reg2, 31, 16)) * 269 sext<16>(bits(Reg3, 31, 16)) + 270 (int64_t)((Reg1.ud << 32) | 271 Reg0.ud); --- 37 unchanged lines hidden (view full) --- 309 (int64_t)Reg2 + 310 ULL(0x80000000)) >> 32; 311 ''') 312 buildMult3InstCc ("smuad", '''Reg0 = resTemp = 313 sext<16>(bits(Reg1, 15, 0)) * 314 sext<16>(bits(Reg2, 15, 0)) + 315 sext<16>(bits(Reg1, 31, 16)) * 316 sext<16>(bits(Reg2, 31, 16)); |
317 resTemp = bits(resTemp, 32) != 318 bits(resTemp, 31); |
319 ''', "overflow") 320 buildMult3InstCc ("smuadx", '''Reg0 = resTemp = 321 sext<16>(bits(Reg1, 15, 0)) * 322 sext<16>(bits(Reg2, 31, 16)) + 323 sext<16>(bits(Reg1, 31, 16)) * 324 sext<16>(bits(Reg2, 15, 0)); |
325 resTemp = bits(resTemp, 32) != 326 bits(resTemp, 31); |
327 ''', "overflow") 328 buildMult3InstUnCc("smulbb", '''Reg0 = resTemp = 329 sext<16>(bits(Reg1, 15, 0)) * 330 sext<16>(bits(Reg2, 15, 0)); 331 ''') 332 buildMult3InstUnCc("smulbt", '''Reg0 = resTemp = 333 sext<16>(bits(Reg1, 15, 0)) * 334 sext<16>(bits(Reg2, 31, 16)); --- 49 unchanged lines hidden --- |