1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcQCode = '''
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcQCode = '''
|
47 cprintf("canOverflow: %%d\\n", Reg0 < resTemp);
48 replaceBits(CondCodes, 27, Reg0 < resTemp);
| 47 CondCodes = CondCodes | ((resTemp & 1) << 27);
|
49 '''
50
51 calcCcCode = '''
52 uint16_t _iz, _in;
53 _in = (resTemp >> %(negBit)d) & 1;
54 _iz = ((%(zType)s)resTemp == 0);
55
56 CondCodes = _in << 31 | _iz << 30 | (CondCodes & 0x3FFFFFFF);
57
58 DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz);
59 '''
60
61 def buildMultInst(mnem, doCc, unCc, regs, code, flagType):
62 global header_output, decoder_output, exec_output
63 cCode = carryCode[flagType]
64 vCode = overflowCode[flagType]
65 zType = "uint32_t"
66 negBit = 31
67 if flagType == "llbit":
68 zType = "uint64_t"
69 negBit = 63
70 if flagType == "overflow":
71 ccCode = calcQCode
72 else:
73 ccCode = calcCcCode % {
74 "negBit": negBit,
75 "zType": zType
76 }
77
78 if not regs in (3, 4):
79 raise Exception, "Multiplication instructions with %d " + \
80 "registers are not implemented"
81
82 if regs == 3:
83 base = 'Mult3'
84 else:
85 base = 'Mult4'
86
87 Name = mnem.capitalize()
88
89 if unCc:
90 iop = InstObjParams(mnem, Name, base,
91 {"code" : code,
92 "predicate_test": predicateTest})
93 if doCc:
94 iopCc = InstObjParams(mnem + "s", Name + "Cc", base,
95 {"code" : code + ccCode,
96 "predicate_test": predicateTest})
97
98 if regs == 3:
99 declare = Mult3Declare
100 constructor = Mult3Constructor
101 else:
102 declare = Mult4Declare
103 constructor = Mult4Constructor
104
105 if unCc:
106 header_output += declare.subst(iop)
107 decoder_output += constructor.subst(iop)
108 exec_output += PredOpExecute.subst(iop)
109 if doCc:
110 header_output += declare.subst(iopCc)
111 decoder_output += constructor.subst(iopCc)
112 exec_output += PredOpExecute.subst(iopCc)
113
114 def buildMult3Inst(mnem, code, flagType = "logic"):
115 buildMultInst(mnem, True, True, 3, code, flagType)
116
117 def buildMult3InstCc(mnem, code, flagType = "logic"):
118 buildMultInst(mnem, True, False, 3, code, flagType)
119
120 def buildMult3InstUnCc(mnem, code, flagType = "logic"):
121 buildMultInst(mnem, False, True, 3, code, flagType)
122
123 def buildMult4Inst(mnem, code, flagType = "logic"):
124 buildMultInst(mnem, True, True, 4, code, flagType)
125
126 def buildMult4InstCc(mnem, code, flagType = "logic"):
127 buildMultInst(mnem, True, False, 4, code, flagType)
128
129 def buildMult4InstUnCc(mnem, code, flagType = "logic"):
130 buildMultInst(mnem, False, True, 4, code, flagType)
131
132 buildMult4Inst ("mla", "Reg0 = resTemp = Reg1 * Reg2 + Reg3;")
133 buildMult4InstUnCc("mls", "Reg0 = resTemp = Reg3 - Reg1 * Reg2;")
134 buildMult3Inst ("mul", "Reg0 = resTemp = Reg1 * Reg2;")
135 buildMult4InstCc ("smlabb", '''Reg0 = resTemp =
136 sext<16>(bits(Reg1, 15, 0)) *
| 48 '''
49
50 calcCcCode = '''
51 uint16_t _iz, _in;
52 _in = (resTemp >> %(negBit)d) & 1;
53 _iz = ((%(zType)s)resTemp == 0);
54
55 CondCodes = _in << 31 | _iz << 30 | (CondCodes & 0x3FFFFFFF);
56
57 DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz);
58 '''
59
60 def buildMultInst(mnem, doCc, unCc, regs, code, flagType):
61 global header_output, decoder_output, exec_output
62 cCode = carryCode[flagType]
63 vCode = overflowCode[flagType]
64 zType = "uint32_t"
65 negBit = 31
66 if flagType == "llbit":
67 zType = "uint64_t"
68 negBit = 63
69 if flagType == "overflow":
70 ccCode = calcQCode
71 else:
72 ccCode = calcCcCode % {
73 "negBit": negBit,
74 "zType": zType
75 }
76
77 if not regs in (3, 4):
78 raise Exception, "Multiplication instructions with %d " + \
79 "registers are not implemented"
80
81 if regs == 3:
82 base = 'Mult3'
83 else:
84 base = 'Mult4'
85
86 Name = mnem.capitalize()
87
88 if unCc:
89 iop = InstObjParams(mnem, Name, base,
90 {"code" : code,
91 "predicate_test": predicateTest})
92 if doCc:
93 iopCc = InstObjParams(mnem + "s", Name + "Cc", base,
94 {"code" : code + ccCode,
95 "predicate_test": predicateTest})
96
97 if regs == 3:
98 declare = Mult3Declare
99 constructor = Mult3Constructor
100 else:
101 declare = Mult4Declare
102 constructor = Mult4Constructor
103
104 if unCc:
105 header_output += declare.subst(iop)
106 decoder_output += constructor.subst(iop)
107 exec_output += PredOpExecute.subst(iop)
108 if doCc:
109 header_output += declare.subst(iopCc)
110 decoder_output += constructor.subst(iopCc)
111 exec_output += PredOpExecute.subst(iopCc)
112
113 def buildMult3Inst(mnem, code, flagType = "logic"):
114 buildMultInst(mnem, True, True, 3, code, flagType)
115
116 def buildMult3InstCc(mnem, code, flagType = "logic"):
117 buildMultInst(mnem, True, False, 3, code, flagType)
118
119 def buildMult3InstUnCc(mnem, code, flagType = "logic"):
120 buildMultInst(mnem, False, True, 3, code, flagType)
121
122 def buildMult4Inst(mnem, code, flagType = "logic"):
123 buildMultInst(mnem, True, True, 4, code, flagType)
124
125 def buildMult4InstCc(mnem, code, flagType = "logic"):
126 buildMultInst(mnem, True, False, 4, code, flagType)
127
128 def buildMult4InstUnCc(mnem, code, flagType = "logic"):
129 buildMultInst(mnem, False, True, 4, code, flagType)
130
131 buildMult4Inst ("mla", "Reg0 = resTemp = Reg1 * Reg2 + Reg3;")
132 buildMult4InstUnCc("mls", "Reg0 = resTemp = Reg3 - Reg1 * Reg2;")
133 buildMult3Inst ("mul", "Reg0 = resTemp = Reg1 * Reg2;")
134 buildMult4InstCc ("smlabb", '''Reg0 = resTemp =
135 sext<16>(bits(Reg1, 15, 0)) *
|
137 sext<16>(bits(Reg2, 15, 0)) +
| 136 sext<16>(bits(Reg2.sw, 15, 0)) +
|
138 Reg3.sw;
| 137 Reg3.sw;
|
| 138 resTemp = bits(resTemp, 32) !=
139 bits(resTemp, 31);
|
139 ''', "overflow")
140 buildMult4InstCc ("smlabt", '''Reg0 = resTemp =
141 sext<16>(bits(Reg1, 15, 0)) *
| 140 ''', "overflow")
141 buildMult4InstCc ("smlabt", '''Reg0 = resTemp =
142 sext<16>(bits(Reg1, 15, 0)) *
|
142 sext<16>(bits(Reg2, 31, 16)) +
| 143 sext<16>(bits(Reg2.sw, 31, 16)) +
|
143 Reg3.sw;
| 144 Reg3.sw;
|
| 145 resTemp = bits(resTemp, 32) !=
146 bits(resTemp, 31);
|
144 ''', "overflow")
145 buildMult4InstCc ("smlatb", '''Reg0 = resTemp =
146 sext<16>(bits(Reg1, 31, 16)) *
| 147 ''', "overflow")
148 buildMult4InstCc ("smlatb", '''Reg0 = resTemp =
149 sext<16>(bits(Reg1, 31, 16)) *
|
147 sext<16>(bits(Reg2, 15, 0)) +
| 150 sext<16>(bits(Reg2.sw, 15, 0)) +
|
148 Reg3.sw;
| 151 Reg3.sw;
|
| 152 resTemp = bits(resTemp, 32) !=
153 bits(resTemp, 31);
|
149 ''', "overflow")
150 buildMult4InstCc ("smlatt", '''Reg0 = resTemp =
151 sext<16>(bits(Reg1, 31, 16)) *
| 154 ''', "overflow")
155 buildMult4InstCc ("smlatt", '''Reg0 = resTemp =
156 sext<16>(bits(Reg1, 31, 16)) *
|
152 sext<16>(bits(Reg2, 31, 16)) +
| 157 sext<16>(bits(Reg2.sw, 31, 16)) +
|
153 Reg3.sw;
| 158 Reg3.sw;
|
| 159 resTemp = bits(resTemp, 32) !=
160 bits(resTemp, 31);
|
154 ''', "overflow")
155 buildMult4InstCc ("smlad", '''Reg0 = resTemp =
156 sext<16>(bits(Reg1, 31, 16)) *
157 sext<16>(bits(Reg2, 31, 16)) +
158 sext<16>(bits(Reg1, 15, 0)) *
159 sext<16>(bits(Reg2, 15, 0)) +
160 Reg3.sw;
161 ''', "overflow")
162 buildMult4InstCc ("smladx", '''Reg0 = resTemp =
163 sext<16>(bits(Reg1, 31, 16)) *
164 sext<16>(bits(Reg2, 15, 0)) +
165 sext<16>(bits(Reg1, 15, 0)) *
166 sext<16>(bits(Reg2, 31, 16)) +
167 Reg3.sw;
168 ''', "overflow")
169 buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) +
170 (int64_t)((Reg1.ud << 32) | Reg0.ud);
171 Reg0.ud = (uint32_t)resTemp;
172 Reg1.ud = (uint32_t)(resTemp >> 32);
173 ''', "llbit")
174 buildMult4InstUnCc("smlalbb", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
175 sext<16>(bits(Reg3, 15, 0)) +
176 (int64_t)((Reg1.ud << 32) |
177 Reg0.ud);
178 Reg0.ud = (uint32_t)resTemp;
179 Reg1.ud = (uint32_t)(resTemp >> 32);
180 ''')
181 buildMult4InstUnCc("smlalbt", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
182 sext<16>(bits(Reg3, 31, 16)) +
183 (int64_t)((Reg1.ud << 32) |
184 Reg0.ud);
185 Reg0.ud = (uint32_t)resTemp;
186 Reg1.ud = (uint32_t)(resTemp >> 32);
187 ''')
188 buildMult4InstUnCc("smlaltb", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
189 sext<16>(bits(Reg3, 15, 0)) +
190 (int64_t)((Reg1.ud << 32) |
191 Reg0.ud);
192 Reg0.ud = (uint32_t)resTemp;
193 Reg1.ud = (uint32_t)(resTemp >> 32);
194 ''')
195 buildMult4InstUnCc("smlaltt", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
196 sext<16>(bits(Reg3, 31, 16)) +
197 (int64_t)((Reg1.ud << 32) |
198 Reg0.ud);
199 Reg0.ud = (uint32_t)resTemp;
200 Reg1.ud = (uint32_t)(resTemp >> 32);
201 ''')
202 buildMult4InstUnCc("smlald", '''resTemp =
203 sext<16>(bits(Reg2, 31, 16)) *
204 sext<16>(bits(Reg3, 31, 16)) +
205 sext<16>(bits(Reg2, 15, 0)) *
206 sext<16>(bits(Reg3, 15, 0)) +
207 (int64_t)((Reg1.ud << 32) |
208 Reg0.ud);
209 Reg0.ud = (uint32_t)resTemp;
210 Reg1.ud = (uint32_t)(resTemp >> 32);
211 ''')
212 buildMult4InstUnCc("smlaldx", '''resTemp =
213 sext<16>(bits(Reg2, 31, 16)) *
214 sext<16>(bits(Reg3, 15, 0)) +
215 sext<16>(bits(Reg2, 15, 0)) *
216 sext<16>(bits(Reg3, 31, 16)) +
217 (int64_t)((Reg1.ud << 32) |
218 Reg0.ud);
219 Reg0.ud = (uint32_t)resTemp;
220 Reg1.ud = (uint32_t)(resTemp >> 32);
221 ''')
222 buildMult4InstCc ("smlawb", '''Reg0 = resTemp =
223 (Reg1.sw *
224 sext<16>(bits(Reg2, 15, 0)) +
| 161 ''', "overflow")
162 buildMult4InstCc ("smlad", '''Reg0 = resTemp =
163 sext<16>(bits(Reg1, 31, 16)) *
164 sext<16>(bits(Reg2, 31, 16)) +
165 sext<16>(bits(Reg1, 15, 0)) *
166 sext<16>(bits(Reg2, 15, 0)) +
167 Reg3.sw;
168 ''', "overflow")
169 buildMult4InstCc ("smladx", '''Reg0 = resTemp =
170 sext<16>(bits(Reg1, 31, 16)) *
171 sext<16>(bits(Reg2, 15, 0)) +
172 sext<16>(bits(Reg1, 15, 0)) *
173 sext<16>(bits(Reg2, 31, 16)) +
174 Reg3.sw;
175 ''', "overflow")
176 buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) +
177 (int64_t)((Reg1.ud << 32) | Reg0.ud);
178 Reg0.ud = (uint32_t)resTemp;
179 Reg1.ud = (uint32_t)(resTemp >> 32);
180 ''', "llbit")
181 buildMult4InstUnCc("smlalbb", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
182 sext<16>(bits(Reg3, 15, 0)) +
183 (int64_t)((Reg1.ud << 32) |
184 Reg0.ud);
185 Reg0.ud = (uint32_t)resTemp;
186 Reg1.ud = (uint32_t)(resTemp >> 32);
187 ''')
188 buildMult4InstUnCc("smlalbt", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
189 sext<16>(bits(Reg3, 31, 16)) +
190 (int64_t)((Reg1.ud << 32) |
191 Reg0.ud);
192 Reg0.ud = (uint32_t)resTemp;
193 Reg1.ud = (uint32_t)(resTemp >> 32);
194 ''')
195 buildMult4InstUnCc("smlaltb", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
196 sext<16>(bits(Reg3, 15, 0)) +
197 (int64_t)((Reg1.ud << 32) |
198 Reg0.ud);
199 Reg0.ud = (uint32_t)resTemp;
200 Reg1.ud = (uint32_t)(resTemp >> 32);
201 ''')
202 buildMult4InstUnCc("smlaltt", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
203 sext<16>(bits(Reg3, 31, 16)) +
204 (int64_t)((Reg1.ud << 32) |
205 Reg0.ud);
206 Reg0.ud = (uint32_t)resTemp;
207 Reg1.ud = (uint32_t)(resTemp >> 32);
208 ''')
209 buildMult4InstUnCc("smlald", '''resTemp =
210 sext<16>(bits(Reg2, 31, 16)) *
211 sext<16>(bits(Reg3, 31, 16)) +
212 sext<16>(bits(Reg2, 15, 0)) *
213 sext<16>(bits(Reg3, 15, 0)) +
214 (int64_t)((Reg1.ud << 32) |
215 Reg0.ud);
216 Reg0.ud = (uint32_t)resTemp;
217 Reg1.ud = (uint32_t)(resTemp >> 32);
218 ''')
219 buildMult4InstUnCc("smlaldx", '''resTemp =
220 sext<16>(bits(Reg2, 31, 16)) *
221 sext<16>(bits(Reg3, 15, 0)) +
222 sext<16>(bits(Reg2, 15, 0)) *
223 sext<16>(bits(Reg3, 31, 16)) +
224 (int64_t)((Reg1.ud << 32) |
225 Reg0.ud);
226 Reg0.ud = (uint32_t)resTemp;
227 Reg1.ud = (uint32_t)(resTemp >> 32);
228 ''')
229 buildMult4InstCc ("smlawb", '''Reg0 = resTemp =
230 (Reg1.sw *
231 sext<16>(bits(Reg2, 15, 0)) +
|
225 (Reg3.sw << 16)) >> 16;
| 232 ((int64_t)Reg3.sw << 16)) >> 16;
233 resTemp = bits(resTemp, 32) !=
234 bits(resTemp, 31);
|
226 ''', "overflow")
227 buildMult4InstCc ("smlawt", '''Reg0 = resTemp =
228 (Reg1.sw *
229 sext<16>(bits(Reg2, 31, 16)) +
| 235 ''', "overflow")
236 buildMult4InstCc ("smlawt", '''Reg0 = resTemp =
237 (Reg1.sw *
238 sext<16>(bits(Reg2, 31, 16)) +
|
230 (Reg3.sw << 16)) >> 16;
| 239 ((int64_t)Reg3.sw << 16)) >> 16;
240 resTemp = bits(resTemp, 32) !=
241 bits(resTemp, 31);
|
231 ''', "overflow")
232 buildMult4InstCc ("smlsd", '''Reg0 = resTemp =
233 sext<16>(bits(Reg1, 15, 0)) *
234 sext<16>(bits(Reg2, 15, 0)) -
235 sext<16>(bits(Reg1, 31, 16)) *
236 sext<16>(bits(Reg2, 31, 16)) +
237 Reg3.sw;
238 ''', "overflow")
239 buildMult4InstCc ("smlsdx", '''Reg0 = resTemp =
240 sext<16>(bits(Reg1, 15, 0)) *
241 sext<16>(bits(Reg2, 31, 16)) -
242 sext<16>(bits(Reg1, 31, 16)) *
243 sext<16>(bits(Reg2, 15, 0)) +
244 Reg3.sw;
245 ''', "overflow")
246 buildMult4InstUnCc("smlsld", '''resTemp =
247 sext<16>(bits(Reg2, 15, 0)) *
248 sext<16>(bits(Reg3, 15, 0)) -
249 sext<16>(bits(Reg2, 31, 16)) *
250 sext<16>(bits(Reg3, 31, 16)) +
251 (int64_t)((Reg1.ud << 32) |
252 Reg0.ud);
253 Reg0.ud = (uint32_t)resTemp;
254 Reg1.ud = (uint32_t)(resTemp >> 32);
255 ''')
256 buildMult4InstUnCc("smlsldx", '''resTemp =
257 sext<16>(bits(Reg2, 15, 0)) *
258 sext<16>(bits(Reg3, 31, 16)) -
259 sext<16>(bits(Reg2, 31, 16)) *
260 sext<16>(bits(Reg3, 15, 0)) +
261 (int64_t)((Reg1.ud << 32) |
262 Reg0.ud);
263 Reg0.ud = (uint32_t)resTemp;
264 Reg1.ud = (uint32_t)(resTemp >> 32);
265 ''')
266 buildMult4InstUnCc("smmla", '''Reg0 = resTemp =
267 ((int64_t)(Reg3.ud << 32) +
268 Reg1.sw * Reg2.sw) >> 32;
269 ''')
270 buildMult4InstUnCc("smmlar", '''Reg0 = resTemp =
271 ((int64_t)(Reg3.ud << 32) +
272 Reg1.sw * Reg2.sw +
273 ULL(0x80000000)) >> 32;
274 ''')
275 buildMult4InstUnCc("smmls", '''Reg0 = resTemp =
276 ((int64_t)(Reg3.ud << 32) -
277 Reg1.sw * Reg2.sw) >> 32;
278 ''')
279 buildMult4InstUnCc("smmlsr", '''Reg0 = resTemp =
280 ((int64_t)(Reg3.ud << 32) -
281 Reg1.sw * Reg2.sw +
282 ULL(0x80000000)) >> 32;
283 ''')
284 buildMult3InstUnCc("smmul", '''Reg0 = resTemp =
285 ((int64_t)Reg1 *
286 (int64_t)Reg2) >> 32;
287 ''')
288 buildMult3InstUnCc("smmulr", '''Reg0 = resTemp =
289 ((int64_t)Reg1 *
290 (int64_t)Reg2 +
291 ULL(0x80000000)) >> 32;
292 ''')
293 buildMult3InstCc ("smuad", '''Reg0 = resTemp =
294 sext<16>(bits(Reg1, 15, 0)) *
295 sext<16>(bits(Reg2, 15, 0)) +
296 sext<16>(bits(Reg1, 31, 16)) *
297 sext<16>(bits(Reg2, 31, 16));
298 ''', "overflow")
299 buildMult3InstCc ("smuadx", '''Reg0 = resTemp =
300 sext<16>(bits(Reg1, 15, 0)) *
301 sext<16>(bits(Reg2, 31, 16)) +
302 sext<16>(bits(Reg1, 31, 16)) *
303 sext<16>(bits(Reg2, 15, 0));
304 ''', "overflow")
305 buildMult3InstUnCc("smulbb", '''Reg0 = resTemp =
306 sext<16>(bits(Reg1, 15, 0)) *
307 sext<16>(bits(Reg2, 15, 0));
308 ''')
309 buildMult3InstUnCc("smulbt", '''Reg0 = resTemp =
| 242 ''', "overflow")
243 buildMult4InstCc ("smlsd", '''Reg0 = resTemp =
244 sext<16>(bits(Reg1, 15, 0)) *
245 sext<16>(bits(Reg2, 15, 0)) -
246 sext<16>(bits(Reg1, 31, 16)) *
247 sext<16>(bits(Reg2, 31, 16)) +
248 Reg3.sw;
249 ''', "overflow")
250 buildMult4InstCc ("smlsdx", '''Reg0 = resTemp =
251 sext<16>(bits(Reg1, 15, 0)) *
252 sext<16>(bits(Reg2, 31, 16)) -
253 sext<16>(bits(Reg1, 31, 16)) *
254 sext<16>(bits(Reg2, 15, 0)) +
255 Reg3.sw;
256 ''', "overflow")
257 buildMult4InstUnCc("smlsld", '''resTemp =
258 sext<16>(bits(Reg2, 15, 0)) *
259 sext<16>(bits(Reg3, 15, 0)) -
260 sext<16>(bits(Reg2, 31, 16)) *
261 sext<16>(bits(Reg3, 31, 16)) +
262 (int64_t)((Reg1.ud << 32) |
263 Reg0.ud);
264 Reg0.ud = (uint32_t)resTemp;
265 Reg1.ud = (uint32_t)(resTemp >> 32);
266 ''')
267 buildMult4InstUnCc("smlsldx", '''resTemp =
268 sext<16>(bits(Reg2, 15, 0)) *
269 sext<16>(bits(Reg3, 31, 16)) -
270 sext<16>(bits(Reg2, 31, 16)) *
271 sext<16>(bits(Reg3, 15, 0)) +
272 (int64_t)((Reg1.ud << 32) |
273 Reg0.ud);
274 Reg0.ud = (uint32_t)resTemp;
275 Reg1.ud = (uint32_t)(resTemp >> 32);
276 ''')
277 buildMult4InstUnCc("smmla", '''Reg0 = resTemp =
278 ((int64_t)(Reg3.ud << 32) +
279 Reg1.sw * Reg2.sw) >> 32;
280 ''')
281 buildMult4InstUnCc("smmlar", '''Reg0 = resTemp =
282 ((int64_t)(Reg3.ud << 32) +
283 Reg1.sw * Reg2.sw +
284 ULL(0x80000000)) >> 32;
285 ''')
286 buildMult4InstUnCc("smmls", '''Reg0 = resTemp =
287 ((int64_t)(Reg3.ud << 32) -
288 Reg1.sw * Reg2.sw) >> 32;
289 ''')
290 buildMult4InstUnCc("smmlsr", '''Reg0 = resTemp =
291 ((int64_t)(Reg3.ud << 32) -
292 Reg1.sw * Reg2.sw +
293 ULL(0x80000000)) >> 32;
294 ''')
295 buildMult3InstUnCc("smmul", '''Reg0 = resTemp =
296 ((int64_t)Reg1 *
297 (int64_t)Reg2) >> 32;
298 ''')
299 buildMult3InstUnCc("smmulr", '''Reg0 = resTemp =
300 ((int64_t)Reg1 *
301 (int64_t)Reg2 +
302 ULL(0x80000000)) >> 32;
303 ''')
304 buildMult3InstCc ("smuad", '''Reg0 = resTemp =
305 sext<16>(bits(Reg1, 15, 0)) *
306 sext<16>(bits(Reg2, 15, 0)) +
307 sext<16>(bits(Reg1, 31, 16)) *
308 sext<16>(bits(Reg2, 31, 16));
309 ''', "overflow")
310 buildMult3InstCc ("smuadx", '''Reg0 = resTemp =
311 sext<16>(bits(Reg1, 15, 0)) *
312 sext<16>(bits(Reg2, 31, 16)) +
313 sext<16>(bits(Reg1, 31, 16)) *
314 sext<16>(bits(Reg2, 15, 0));
315 ''', "overflow")
316 buildMult3InstUnCc("smulbb", '''Reg0 = resTemp =
317 sext<16>(bits(Reg1, 15, 0)) *
318 sext<16>(bits(Reg2, 15, 0));
319 ''')
320 buildMult3InstUnCc("smulbt", '''Reg0 = resTemp =
|
310 sext<16>(bits(Reg1, 31, 16)) *
311 sext<16>(bits(Reg2, 15, 0));
312 ''')
313 buildMult3InstUnCc("smultb", '''Reg0 = resTemp =
| |
314 sext<16>(bits(Reg1, 15, 0)) *
315 sext<16>(bits(Reg2, 31, 16));
316 ''')
| 321 sext<16>(bits(Reg1, 15, 0)) *
322 sext<16>(bits(Reg2, 31, 16));
323 ''')
|
| 324 buildMult3InstUnCc("smultb", '''Reg0 = resTemp =
325 sext<16>(bits(Reg1, 31, 16)) *
326 sext<16>(bits(Reg2, 15, 0));
327 ''')
|
317 buildMult3InstUnCc("smultt", '''Reg0 = resTemp =
318 sext<16>(bits(Reg1, 31, 16)) *
319 sext<16>(bits(Reg2, 31, 16));
320 ''')
| 328 buildMult3InstUnCc("smultt", '''Reg0 = resTemp =
329 sext<16>(bits(Reg1, 31, 16)) *
330 sext<16>(bits(Reg2, 31, 16));
331 ''')
|
321 buildMult4Inst ("smull", '''resTemp = Reg2.sw * Reg3.sw;
| 332 buildMult4Inst ("smull", '''resTemp = (int64_t)Reg2.sw *
333 (int64_t)Reg3.sw;
|
322 Reg0 = (int32_t)resTemp;
323 Reg1 = (int32_t)(resTemp >> 32);
324 ''', "llbit")
325 buildMult3InstUnCc("smulwb", '''Reg0 = resTemp =
326 (Reg1.sw *
327 sext<16>(bits(Reg2, 15, 0))) >> 16;
328 ''')
329 buildMult3InstUnCc("smulwt", '''Reg0 = resTemp =
330 (Reg1.sw *
331 sext<16>(bits(Reg2, 31, 16))) >> 16;
332 ''')
333 buildMult3InstUnCc("smusd", '''Reg0 = resTemp =
334 sext<16>(bits(Reg1, 15, 0)) *
335 sext<16>(bits(Reg2, 15, 0)) -
336 sext<16>(bits(Reg1, 31, 16)) *
337 sext<16>(bits(Reg2, 31, 16));
338 ''')
339 buildMult3InstUnCc("smusdx", '''Reg0 = resTemp =
340 sext<16>(bits(Reg1, 15, 0)) *
341 sext<16>(bits(Reg2, 31, 16)) -
342 sext<16>(bits(Reg1, 31, 16)) *
343 sext<16>(bits(Reg2, 15, 0));
344 ''')
345 buildMult4InstUnCc("umaal", '''resTemp = Reg2.ud * Reg3.ud +
346 Reg0.ud + Reg1.ud;
347 Reg0.ud = (uint32_t)resTemp;
348 Reg1.ud = (uint32_t)(resTemp >> 32);
349 ''')
350 buildMult4Inst ("umlal", '''resTemp = Reg2.ud * Reg3.ud + Reg0.ud +
351 (Reg1.ud << 32);
352 Reg0.ud = (uint32_t)resTemp;
353 Reg1.ud = (uint32_t)(resTemp >> 32);
354 ''', "llbit")
355 buildMult4Inst ("umull", '''resTemp = Reg2.ud * Reg3.ud;
356 Reg0 = (uint32_t)resTemp;
357 Reg1 = (uint32_t)(resTemp >> 32);
358 ''', "llbit")
359}};
| 334 Reg0 = (int32_t)resTemp;
335 Reg1 = (int32_t)(resTemp >> 32);
336 ''', "llbit")
337 buildMult3InstUnCc("smulwb", '''Reg0 = resTemp =
338 (Reg1.sw *
339 sext<16>(bits(Reg2, 15, 0))) >> 16;
340 ''')
341 buildMult3InstUnCc("smulwt", '''Reg0 = resTemp =
342 (Reg1.sw *
343 sext<16>(bits(Reg2, 31, 16))) >> 16;
344 ''')
345 buildMult3InstUnCc("smusd", '''Reg0 = resTemp =
346 sext<16>(bits(Reg1, 15, 0)) *
347 sext<16>(bits(Reg2, 15, 0)) -
348 sext<16>(bits(Reg1, 31, 16)) *
349 sext<16>(bits(Reg2, 31, 16));
350 ''')
351 buildMult3InstUnCc("smusdx", '''Reg0 = resTemp =
352 sext<16>(bits(Reg1, 15, 0)) *
353 sext<16>(bits(Reg2, 31, 16)) -
354 sext<16>(bits(Reg1, 31, 16)) *
355 sext<16>(bits(Reg2, 15, 0));
356 ''')
357 buildMult4InstUnCc("umaal", '''resTemp = Reg2.ud * Reg3.ud +
358 Reg0.ud + Reg1.ud;
359 Reg0.ud = (uint32_t)resTemp;
360 Reg1.ud = (uint32_t)(resTemp >> 32);
361 ''')
362 buildMult4Inst ("umlal", '''resTemp = Reg2.ud * Reg3.ud + Reg0.ud +
363 (Reg1.ud << 32);
364 Reg0.ud = (uint32_t)resTemp;
365 Reg1.ud = (uint32_t)(resTemp >> 32);
366 ''', "llbit")
367 buildMult4Inst ("umull", '''resTemp = Reg2.ud * Reg3.ud;
368 Reg0 = (uint32_t)resTemp;
369 Reg1 = (uint32_t)(resTemp >> 32);
370 ''', "llbit")
371}};
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