1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 30 unchanged lines hidden (view full) ---

39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcQCode = '''
47 cprintf("canOverflow: %%d\\n", Reg0 < resTemp);
48 replaceBits(CondCodes, 27, Reg0 < resTemp);
49 '''
50
51 calcCcCode = '''
52 uint16_t _iz, _in;
53 _in = (resTemp >> %(negBit)d) & 1;
54 _iz = ((%(zType)s)resTemp == 0);
55
56 CondCodes = _in << 31 | _iz << 30 | (CondCodes & 0x3FFFFFFF);

--- 72 unchanged lines hidden (view full) ---

129 def buildMult4InstUnCc(mnem, code, flagType = "logic"):
130 buildMultInst(mnem, False, True, 4, code, flagType)
131
132 buildMult4Inst ("mla", "Reg0 = resTemp = Reg1 * Reg2 + Reg3;")
133 buildMult4InstUnCc("mls", "Reg0 = resTemp = Reg3 - Reg1 * Reg2;")
134 buildMult3Inst ("mul", "Reg0 = resTemp = Reg1 * Reg2;")
135 buildMult4InstCc ("smlabb", '''Reg0 = resTemp =
136 sext<16>(bits(Reg1, 15, 0)) *
137 sext<16>(bits(Reg2, 15, 0)) +
138 Reg3.sw;
139 ''', "overflow")
140 buildMult4InstCc ("smlabt", '''Reg0 = resTemp =
141 sext<16>(bits(Reg1, 15, 0)) *
142 sext<16>(bits(Reg2, 31, 16)) +
143 Reg3.sw;
144 ''', "overflow")
145 buildMult4InstCc ("smlatb", '''Reg0 = resTemp =
146 sext<16>(bits(Reg1, 31, 16)) *
147 sext<16>(bits(Reg2, 15, 0)) +
148 Reg3.sw;
149 ''', "overflow")
150 buildMult4InstCc ("smlatt", '''Reg0 = resTemp =
151 sext<16>(bits(Reg1, 31, 16)) *
152 sext<16>(bits(Reg2, 31, 16)) +
153 Reg3.sw;
154 ''', "overflow")
155 buildMult4InstCc ("smlad", '''Reg0 = resTemp =
156 sext<16>(bits(Reg1, 31, 16)) *
157 sext<16>(bits(Reg2, 31, 16)) +
158 sext<16>(bits(Reg1, 15, 0)) *
159 sext<16>(bits(Reg2, 15, 0)) +
160 Reg3.sw;
161 ''', "overflow")

--- 55 unchanged lines hidden (view full) ---

217 (int64_t)((Reg1.ud << 32) |
218 Reg0.ud);
219 Reg0.ud = (uint32_t)resTemp;
220 Reg1.ud = (uint32_t)(resTemp >> 32);
221 ''')
222 buildMult4InstCc ("smlawb", '''Reg0 = resTemp =
223 (Reg1.sw *
224 sext<16>(bits(Reg2, 15, 0)) +
225 (Reg3.sw << 16)) >> 16;
226 ''', "overflow")
227 buildMult4InstCc ("smlawt", '''Reg0 = resTemp =
228 (Reg1.sw *
229 sext<16>(bits(Reg2, 31, 16)) +
230 (Reg3.sw << 16)) >> 16;
231 ''', "overflow")
232 buildMult4InstCc ("smlsd", '''Reg0 = resTemp =
233 sext<16>(bits(Reg1, 15, 0)) *
234 sext<16>(bits(Reg2, 15, 0)) -
235 sext<16>(bits(Reg1, 31, 16)) *
236 sext<16>(bits(Reg2, 31, 16)) +
237 Reg3.sw;
238 ''', "overflow")

--- 63 unchanged lines hidden (view full) ---

302 sext<16>(bits(Reg1, 31, 16)) *
303 sext<16>(bits(Reg2, 15, 0));
304 ''', "overflow")
305 buildMult3InstUnCc("smulbb", '''Reg0 = resTemp =
306 sext<16>(bits(Reg1, 15, 0)) *
307 sext<16>(bits(Reg2, 15, 0));
308 ''')
309 buildMult3InstUnCc("smulbt", '''Reg0 = resTemp =
310 sext<16>(bits(Reg1, 31, 16)) *
311 sext<16>(bits(Reg2, 15, 0));
312 ''')
313 buildMult3InstUnCc("smultb", '''Reg0 = resTemp =
314 sext<16>(bits(Reg1, 15, 0)) *
315 sext<16>(bits(Reg2, 31, 16));
316 ''')
317 buildMult3InstUnCc("smultt", '''Reg0 = resTemp =
318 sext<16>(bits(Reg1, 31, 16)) *
319 sext<16>(bits(Reg2, 31, 16));
320 ''')
321 buildMult4Inst ("smull", '''resTemp = Reg2.sw * Reg3.sw;
322 Reg0 = (int32_t)resTemp;
323 Reg1 = (int32_t)(resTemp >> 32);
324 ''', "llbit")
325 buildMult3InstUnCc("smulwb", '''Reg0 = resTemp =
326 (Reg1.sw *
327 sext<16>(bits(Reg2, 15, 0))) >> 16;
328 ''')
329 buildMult3InstUnCc("smulwt", '''Reg0 = resTemp =

--- 30 unchanged lines hidden ---