misc64.isa (12538:001ad6b1e592) misc64.isa (12539:14f557f1dab8)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 163 unchanged lines hidden (view full) ---

172 brkIop = InstObjParams("brk", "Brk64", "ImmOp64",
173 brkCode, ["IsSerializeAfter"])
174 header_output += ImmOp64Declare.subst(brkIop)
175 decoder_output += ImmOp64Constructor.subst(brkIop)
176 exec_output += BasicExecute.subst(brkIop)
177
178 hltCode = '''
179 ThreadContext *tc = xc->tcBase();
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 163 unchanged lines hidden (view full) ---

172 brkIop = InstObjParams("brk", "Brk64", "ImmOp64",
173 brkCode, ["IsSerializeAfter"])
174 header_output += ImmOp64Declare.subst(brkIop)
175 decoder_output += ImmOp64Constructor.subst(brkIop)
176 exec_output += BasicExecute.subst(brkIop)
177
178 hltCode = '''
179 ThreadContext *tc = xc->tcBase();
180 if (ArmSystem::haveSemihosting(tc) && bits(machInst, 20, 5) == 0xF000) {
180 if (ArmSystem::haveSemihosting(tc) && imm == 0xF000) {
181 X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1);
182 } else {
183 // HLT instructions aren't implemented, so treat them as undefined
184 // instructions.
185 fault = std::make_shared<UndefinedInstruction>(
186 machInst, false, mnemonic);
187 }
188
189 '''
190
191 hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64",
192 hltCode, ["IsNonSpeculative"])
193 header_output += ImmOp64Declare.subst(hltIop)
194 decoder_output += ImmOp64Constructor.subst(hltIop)
195 exec_output += BasicExecute.subst(hltIop)
196}};
181 X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1);
182 } else {
183 // HLT instructions aren't implemented, so treat them as undefined
184 // instructions.
185 fault = std::make_shared<UndefinedInstruction>(
186 machInst, false, mnemonic);
187 }
188
189 '''
190
191 hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64",
192 hltCode, ["IsNonSpeculative"])
193 header_output += ImmOp64Declare.subst(hltIop)
194 decoder_output += ImmOp64Constructor.subst(hltIop)
195 exec_output += BasicExecute.subst(hltIop)
196}};