misc64.isa (10537:47fe87b0cf97) | misc64.isa (11576:9ff589e30935) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2011-2013 ARM Limited | 3// Copyright (c) 2011-2013, 2016 ARM Limited |
4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 32 unchanged lines hidden (view full) --- 44 45 svcIop = InstObjParams("svc", "Svc64", "ArmStaticInst", 46 svcCode, ["IsSyscall", "IsNonSpeculative", 47 "IsSerializeAfter"]) 48 header_output = BasicDeclare.subst(svcIop) 49 decoder_output = BasicConstructor64.subst(svcIop) 50 exec_output = BasicExecute.subst(svcIop) 51 | 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 32 unchanged lines hidden (view full) --- 44 45 svcIop = InstObjParams("svc", "Svc64", "ArmStaticInst", 46 svcCode, ["IsSyscall", "IsNonSpeculative", 47 "IsSerializeAfter"]) 48 header_output = BasicDeclare.subst(svcIop) 49 decoder_output = BasicConstructor64.subst(svcIop) 50 exec_output = BasicExecute.subst(svcIop) 51 |
52 hvcCode = ''' 53 SCR scr = Scr64; 54 55 if (!ArmSystem::haveVirtualization(xc->tcBase()) || 56 (ArmSystem::haveSecurity(xc->tcBase()) && !scr.hce)) { 57 fault = disabledFault(); 58 } else { 59 fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5)); 60 } 61 ''' 62 63 hvcIop = InstObjParams("hvc", "Hvc64", "ArmStaticInst", 64 hvcCode, ["IsSyscall", "IsNonSpeculative", 65 "IsSerializeAfter"]) 66 header_output += BasicDeclare.subst(hvcIop) 67 decoder_output += BasicConstructor64.subst(hvcIop) 68 exec_output += BasicExecute.subst(hvcIop) 69 |
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52 # @todo: extend to take into account Virtualization. 53 smcCode = ''' 54 SCR scr = Scr64; 55 CPSR cpsr = Cpsr; 56 57 if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) || scr.smd) { 58 fault = disabledFault(); 59 } else { --- 90 unchanged lines hidden --- | 70 # @todo: extend to take into account Virtualization. 71 smcCode = ''' 72 SCR scr = Scr64; 73 CPSR cpsr = Cpsr; 74 75 if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) || scr.smd) { 76 fault = disabledFault(); 77 } else { --- 90 unchanged lines hidden --- |