1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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46 svcCode, ["IsSyscall", "IsNonSpeculative",
47 "IsSerializeAfter"])
48 header_output = ImmOp64Declare.subst(svcIop)
49 decoder_output = ImmOp64Constructor.subst(svcIop)
50 exec_output = BasicExecute.subst(svcIop)
51
52 hvcCode = '''
53 SCR scr = Scr64;
54
55 if (!ArmSystem::haveVirtualization(xc->tcBase()) ||
56 (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
57 fault = disabledFault();
58 } else {
59 fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5));
60 }
61 '''
62
63 hvcIop = InstObjParams("hvc", "Hvc64", "ImmOp64",
64 hvcCode, ["IsSyscall", "IsNonSpeculative",
65 "IsSerializeAfter"])

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