misc.isa (8908:412877977866) misc.isa (10037:5cac77888310)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2012 ARM Limited
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 23 unchanged lines hidden (view full) ---

35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 svcCode = '''
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 23 unchanged lines hidden (view full) ---

35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 svcCode = '''
43 if (FullSystem) {
44 fault = new SupervisorCall;
45 } else {
46 fault = new SupervisorCall(machInst);
47 }
43 fault = new SupervisorCall(machInst, imm);
48 '''
49
44 '''
45
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
46 svcIop = InstObjParams("svc", "Svc", "ImmOp",
51 { "code": svcCode,
52 "predicate_test": predicateTest },
53 ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
47 { "code": svcCode,
48 "predicate_test": predicateTest },
49 ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
54 header_output = BasicDeclare.subst(svcIop)
55 decoder_output = BasicConstructor.subst(svcIop)
50 header_output = ImmOpDeclare.subst(svcIop)
51 decoder_output = ImmOpConstructor.subst(svcIop)
56 exec_output = PredOpExecute.subst(svcIop)
57
52 exec_output = PredOpExecute.subst(svcIop)
53
54 smcCode = '''
55 HCR hcr = Hcr;
56 CPSR cpsr = Cpsr;
57 SCR scr = Scr;
58
59 if ((cpsr.mode != MODE_USER) && FullSystem) {
60 if (ArmSystem::haveVirtualization(xc->tcBase()) &&
61 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
62 fault = new HypervisorTrap(machInst, 0, EC_SMC_TO_HYP);
63 } else {
64 if (scr.scd) {
65 fault = disabledFault();
66 } else {
67 fault = new SecureMonitorCall(machInst);
68 }
69 }
70 } else {
71 fault = disabledFault();
72 }
73 '''
74
75 smcIop = InstObjParams("smc", "Smc", "PredOp",
76 { "code": smcCode,
77 "predicate_test": predicateTest },
78 ["IsNonSpeculative", "IsSerializeAfter"])
79 header_output += BasicDeclare.subst(smcIop)
80 decoder_output += BasicConstructor.subst(smcIop)
81 exec_output += PredOpExecute.subst(smcIop)
82
83 hvcCode = '''
84 CPSR cpsr = Cpsr;
85 SCR scr = Scr;
86
87 // Filter out the various cases where this instruction isn't defined
88 if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
89 (cpsr.mode == MODE_USER) ||
90 (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
91 fault = disabledFault();
92 } else {
93 fault = new HypervisorCall(machInst, imm);
94 }
95 '''
96
97 hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
98 { "code": hvcCode,
99 "predicate_test": predicateTest },
100 ["IsNonSpeculative", "IsSerializeAfter"])
101 header_output += ImmOpDeclare.subst(hvcIop)
102 decoder_output += ImmOpConstructor.subst(hvcIop)
103 exec_output += PredOpExecute.subst(hvcIop)
104
105 eretCode = '''
106 SCTLR sctlr = Sctlr;
107 CPSR old_cpsr = Cpsr;
108 old_cpsr.nz = CondCodesNZ;
109 old_cpsr.c = CondCodesC;
110 old_cpsr.v = CondCodesV;
111 old_cpsr.ge = CondCodesGE;
112
113 CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF,
114 true, sctlr.nmfi, xc->tcBase());
115 Cpsr = ~CondCodesMask & new_cpsr;
116 CondCodesNZ = new_cpsr.nz;
117 CondCodesC = new_cpsr.c;
118 CondCodesV = new_cpsr.v;
119 CondCodesGE = new_cpsr.ge;
120
121 NextThumb = (new_cpsr).t;
122 NextJazelle = (new_cpsr).j;
123 NextItState = (((new_cpsr).it2 << 2) & 0xFC)
124 | ((new_cpsr).it1 & 0x3);
125
126 NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
127 '''
128
129 eretIop = InstObjParams("eret", "Eret", "PredOp",
130 { "code": eretCode,
131 "predicate_test": predicateTest },
132 ["IsNonSpeculative", "IsSerializeAfter"])
133 header_output += BasicDeclare.subst(eretIop)
134 decoder_output += BasicConstructor.subst(eretIop)
135 exec_output += PredOpExecute.subst(eretIop)
136
137
138
58}};
59
60let {{
61
62 header_output = decoder_output = exec_output = ""
63
64 mrsCpsrCode = '''
65 CPSR cpsr = Cpsr;

--- 16 unchanged lines hidden (view full) ---

82 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
83 { "code": mrsSpsrCode,
84 "predicate_test": predicateTest },
85 ["IsSerializeBefore"])
86 header_output += MrsDeclare.subst(mrsSpsrIop)
87 decoder_output += MrsConstructor.subst(mrsSpsrIop)
88 exec_output += PredOpExecute.subst(mrsSpsrIop)
89
139}};
140
141let {{
142
143 header_output = decoder_output = exec_output = ""
144
145 mrsCpsrCode = '''
146 CPSR cpsr = Cpsr;

--- 16 unchanged lines hidden (view full) ---

163 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
164 { "code": mrsSpsrCode,
165 "predicate_test": predicateTest },
166 ["IsSerializeBefore"])
167 header_output += MrsDeclare.subst(mrsSpsrIop)
168 decoder_output += MrsConstructor.subst(mrsSpsrIop)
169 exec_output += PredOpExecute.subst(mrsSpsrIop)
170
171 mrsBankedRegCode = '''
172 bool isIntReg;
173 int regIdx;
174
175 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
176 if (isIntReg) {
177 Dest = DecodedBankedIntReg;
178 } else {
179 Dest = xc->readMiscReg(regIdx);
180 }
181 } else {
182 return new UndefinedInstruction(machInst, false, mnemonic);
183 }
184 '''
185 mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
186 { "code": mrsBankedRegCode,
187 "predicate_test": predicateTest },
188 ["IsSerializeBefore"])
189 header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
190 decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
191 exec_output += PredOpExecute.subst(mrsBankedRegIop)
192
193 msrBankedRegCode = '''
194 bool isIntReg;
195 int regIdx;
196
197 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
198 if (isIntReg) {
199 // This is a bit nasty, you would have thought that
200 // DecodedBankedIntReg wouldn't be written to unless the
201 // conditions on the IF statements above are met, however if
202 // you look at the generated C code you'll find that they are.
203 // However this is safe as DecodedBankedIntReg (which is used
204 // in operands.isa to get the index of DecodedBankedIntReg)
205 // will return INTREG_DUMMY if its not a valid integer
206 // register, so redirecting the write to somewhere we don't
207 // care about.
208 DecodedBankedIntReg = Op1;
209 } else {
210 xc->setMiscReg(regIdx, Op1);
211 }
212 } else {
213 return new UndefinedInstruction(machInst, false, mnemonic);
214 }
215 '''
216 msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
217 { "code": msrBankedRegCode,
218 "predicate_test": predicateTest },
219 ["IsSerializeAfter"])
220 header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
221 decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
222 exec_output += PredOpExecute.subst(msrBankedRegIop)
223
90 msrCpsrRegCode = '''
91 SCTLR sctlr = Sctlr;
92 CPSR old_cpsr = Cpsr;
93 old_cpsr.nz = CondCodesNZ;
94 old_cpsr.c = CondCodesC;
95 old_cpsr.v = CondCodesV;
96 old_cpsr.ge = CondCodesGE;
97
98 CPSR new_cpsr =
224 msrCpsrRegCode = '''
225 SCTLR sctlr = Sctlr;
226 CPSR old_cpsr = Cpsr;
227 old_cpsr.nz = CondCodesNZ;
228 old_cpsr.c = CondCodesC;
229 old_cpsr.v = CondCodesV;
230 old_cpsr.ge = CondCodesGE;
231
232 CPSR new_cpsr =
99 cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi);
233 cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false,
234 sctlr.nmfi, xc->tcBase());
100 Cpsr = ~CondCodesMask & new_cpsr;
101 CondCodesNZ = new_cpsr.nz;
102 CondCodesC = new_cpsr.c;
103 CondCodesV = new_cpsr.v;
104 CondCodesGE = new_cpsr.ge;
105 '''
106 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
107 { "code": msrCpsrRegCode,

--- 15 unchanged lines hidden (view full) ---

123 msrCpsrImmCode = '''
124 SCTLR sctlr = Sctlr;
125 CPSR old_cpsr = Cpsr;
126 old_cpsr.nz = CondCodesNZ;
127 old_cpsr.c = CondCodesC;
128 old_cpsr.v = CondCodesV;
129 old_cpsr.ge = CondCodesGE;
130 CPSR new_cpsr =
235 Cpsr = ~CondCodesMask & new_cpsr;
236 CondCodesNZ = new_cpsr.nz;
237 CondCodesC = new_cpsr.c;
238 CondCodesV = new_cpsr.v;
239 CondCodesGE = new_cpsr.ge;
240 '''
241 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
242 { "code": msrCpsrRegCode,

--- 15 unchanged lines hidden (view full) ---

258 msrCpsrImmCode = '''
259 SCTLR sctlr = Sctlr;
260 CPSR old_cpsr = Cpsr;
261 old_cpsr.nz = CondCodesNZ;
262 old_cpsr.c = CondCodesC;
263 old_cpsr.v = CondCodesV;
264 old_cpsr.ge = CondCodesGE;
265 CPSR new_cpsr =
131 cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi);
266 cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false,
267 sctlr.nmfi, xc->tcBase());
132 Cpsr = ~CondCodesMask & new_cpsr;
133 CondCodesNZ = new_cpsr.nz;
134 CondCodesC = new_cpsr.c;
135 CondCodesV = new_cpsr.v;
136 CondCodesGE = new_cpsr.ge;
137 '''
138 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
139 { "code": msrCpsrImmCode,

--- 343 unchanged lines hidden (view full) ---

483 exec_output += PredOpExecute.subst(usada8Iop)
484
485 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
486 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
487 header_output += BasicDeclare.subst(bkptIop)
488 decoder_output += BasicConstructor.subst(bkptIop)
489 exec_output += BasicExecute.subst(bkptIop)
490
268 Cpsr = ~CondCodesMask & new_cpsr;
269 CondCodesNZ = new_cpsr.nz;
270 CondCodesC = new_cpsr.c;
271 CondCodesV = new_cpsr.v;
272 CondCodesGE = new_cpsr.ge;
273 '''
274 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
275 { "code": msrCpsrImmCode,

--- 343 unchanged lines hidden (view full) ---

619 exec_output += PredOpExecute.subst(usada8Iop)
620
621 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
622 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
623 header_output += BasicDeclare.subst(bkptIop)
624 decoder_output += BasicConstructor.subst(bkptIop)
625 exec_output += BasicExecute.subst(bkptIop)
626
491 nopIop = InstObjParams("nop", "NopInst", "PredOp", \
492 { "code" : "", "predicate_test" : predicateTest },
493 ['IsNop'])
627 nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
494 header_output += BasicDeclare.subst(nopIop)
628 header_output += BasicDeclare.subst(nopIop)
495 decoder_output += BasicConstructor.subst(nopIop)
496 exec_output += PredOpExecute.subst(nopIop)
629 decoder_output += BasicConstructor64.subst(nopIop)
630 exec_output += BasicExecute.subst(nopIop)
497
498 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
499 { "code" : "", "predicate_test" : predicateTest })
500 header_output += BasicDeclare.subst(yieldIop)
501 decoder_output += BasicConstructor.subst(yieldIop)
502 exec_output += PredOpExecute.subst(yieldIop)
503
504 wfeCode = '''
631
632 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
633 { "code" : "", "predicate_test" : predicateTest })
634 header_output += BasicDeclare.subst(yieldIop)
635 decoder_output += BasicConstructor.subst(yieldIop)
636 exec_output += PredOpExecute.subst(yieldIop)
637
638 wfeCode = '''
505 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
639 HCR hcr = Hcr;
640 CPSR cpsr = Cpsr;
641 SCR scr = Scr64;
642 SCTLR sctlr = Sctlr;
643
644 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
645 ThreadContext *tc = xc->tcBase();
506 if (SevMailbox == 1) {
507 SevMailbox = 0;
646 if (SevMailbox == 1) {
647 SevMailbox = 0;
508 PseudoInst::quiesceSkip(xc->tcBase());
509 } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) {
510 PseudoInst::quiesceSkip(xc->tcBase());
648 PseudoInst::quiesceSkip(tc);
649 } else if (tc->getCpuPtr()->getInterruptController()->checkInterrupts(tc)) {
650 PseudoInst::quiesceSkip(tc);
651 } else if (cpsr.el == EL0 && !sctlr.ntwe) {
652 PseudoInst::quiesceSkip(tc);
653 fault = new SupervisorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE);
654 } else if (ArmSystem::haveVirtualization(tc) &&
655 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) &&
656 hcr.twe) {
657 PseudoInst::quiesceSkip(tc);
658 fault = new HypervisorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE);
659 } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twe) {
660 PseudoInst::quiesceSkip(tc);
661 fault = new SecureMonitorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE);
511 } else {
662 } else {
512 PseudoInst::quiesce(xc->tcBase());
663 PseudoInst::quiesce(tc);
513 }
514 '''
515 wfePredFixUpCode = '''
516 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
517 // and SEV interrupts
518 SevMailbox = 1;
519 '''
520 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
521 { "code" : wfeCode,
522 "pred_fixup" : wfePredFixUpCode,
523 "predicate_test" : predicateTest },
524 ["IsNonSpeculative", "IsQuiesce",
525 "IsSerializeAfter", "IsUnverifiable"])
526 header_output += BasicDeclare.subst(wfeIop)
527 decoder_output += BasicConstructor.subst(wfeIop)
528 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
529
530 wfiCode = '''
664 }
665 '''
666 wfePredFixUpCode = '''
667 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
668 // and SEV interrupts
669 SevMailbox = 1;
670 '''
671 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
672 { "code" : wfeCode,
673 "pred_fixup" : wfePredFixUpCode,
674 "predicate_test" : predicateTest },
675 ["IsNonSpeculative", "IsQuiesce",
676 "IsSerializeAfter", "IsUnverifiable"])
677 header_output += BasicDeclare.subst(wfeIop)
678 decoder_output += BasicConstructor.subst(wfeIop)
679 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
680
681 wfiCode = '''
682 HCR hcr = Hcr;
683 CPSR cpsr = Cpsr;
684 SCR scr = Scr64;
685 SCTLR sctlr = Sctlr;
686
531 // WFI doesn't sleep if interrupts are pending (masked or not)
687 // WFI doesn't sleep if interrupts are pending (masked or not)
532 if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
533 PseudoInst::quiesceSkip(xc->tcBase());
688 ThreadContext *tc = xc->tcBase();
689 if (tc->getCpuPtr()->getInterruptController()->checkWfiWake(hcr, cpsr,
690 scr)) {
691 PseudoInst::quiesceSkip(tc);
692 } else if (cpsr.el == EL0 && !sctlr.ntwi) {
693 PseudoInst::quiesceSkip(tc);
694 fault = new SupervisorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE);
695 } else if (ArmSystem::haveVirtualization(tc) && hcr.twi &&
696 (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr)) {
697 PseudoInst::quiesceSkip(tc);
698 fault = new HypervisorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE);
699 } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twi) {
700 PseudoInst::quiesceSkip(tc);
701 fault = new SecureMonitorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE);
534 } else {
702 } else {
535 PseudoInst::quiesce(xc->tcBase());
703 PseudoInst::quiesce(tc);
536 }
704 }
705 tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
537 '''
538 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
539 { "code" : wfiCode, "predicate_test" : predicateTest },
540 ["IsNonSpeculative", "IsQuiesce",
541 "IsSerializeAfter", "IsUnverifiable"])
542 header_output += BasicDeclare.subst(wfiIop)
543 decoder_output += BasicConstructor.subst(wfiIop)
544 exec_output += QuiescePredOpExecute.subst(wfiIop)

--- 14 unchanged lines hidden (view full) ---

559 '''
560 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
561 { "code" : sevCode, "predicate_test" : predicateTest },
562 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
563 header_output += BasicDeclare.subst(sevIop)
564 decoder_output += BasicConstructor.subst(sevIop)
565 exec_output += PredOpExecute.subst(sevIop)
566
706 '''
707 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
708 { "code" : wfiCode, "predicate_test" : predicateTest },
709 ["IsNonSpeculative", "IsQuiesce",
710 "IsSerializeAfter", "IsUnverifiable"])
711 header_output += BasicDeclare.subst(wfiIop)
712 decoder_output += BasicConstructor.subst(wfiIop)
713 exec_output += QuiescePredOpExecute.subst(wfiIop)

--- 14 unchanged lines hidden (view full) ---

728 '''
729 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
730 { "code" : sevCode, "predicate_test" : predicateTest },
731 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
732 header_output += BasicDeclare.subst(sevIop)
733 decoder_output += BasicConstructor.subst(sevIop)
734 exec_output += PredOpExecute.subst(sevIop)
735
736 sevlCode = '''
737 SevMailbox = 1;
738 '''
739 sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
740 { "code" : sevlCode, "predicate_test" : predicateTest },
741 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
742 header_output += BasicDeclare.subst(sevlIop)
743 decoder_output += BasicConstructor.subst(sevlIop)
744 exec_output += BasicExecute.subst(sevlIop)
745
567 itIop = InstObjParams("it", "ItInst", "PredOp", \
568 { "code" : ";",
569 "predicate_test" : predicateTest }, [])
570 header_output += BasicDeclare.subst(itIop)
571 decoder_output += BasicConstructor.subst(itIop)
572 exec_output += PredOpExecute.subst(itIop)
573 unknownCode = '''
746 itIop = InstObjParams("it", "ItInst", "PredOp", \
747 { "code" : ";",
748 "predicate_test" : predicateTest }, [])
749 header_output += BasicDeclare.subst(itIop)
750 decoder_output += BasicConstructor.subst(itIop)
751 exec_output += PredOpExecute.subst(itIop)
752 unknownCode = '''
574 if (FullSystem)
575 return new UndefinedInstruction;
576 else
577 return new UndefinedInstruction(machInst, true);
753 return new UndefinedInstruction(machInst, true);
578 '''
579 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
580 { "code": unknownCode,
581 "predicate_test": predicateTest })
582 header_output += BasicDeclare.subst(unknownIop)
583 decoder_output += BasicConstructor.subst(unknownIop)
584 exec_output += PredOpExecute.subst(unknownIop)
585

--- 35 unchanged lines hidden (view full) ---

621 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
622 { "code": bfiCode,
623 "predicate_test": predicateTest }, [])
624 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
625 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
626 exec_output += PredOpExecute.subst(bfiIop)
627
628 mrc14code = '''
754 '''
755 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
756 { "code": unknownCode,
757 "predicate_test": predicateTest })
758 header_output += BasicDeclare.subst(unknownIop)
759 decoder_output += BasicConstructor.subst(unknownIop)
760 exec_output += PredOpExecute.subst(unknownIop)
761

--- 35 unchanged lines hidden (view full) ---

797 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
798 { "code": bfiCode,
799 "predicate_test": predicateTest }, [])
800 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
801 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
802 exec_output += PredOpExecute.subst(bfiIop)
803
804 mrc14code = '''
629 CPSR cpsr = Cpsr;
630 if (cpsr.mode == MODE_USER) {
631 if (FullSystem)
632 return new UndefinedInstruction;
633 else
634 return new UndefinedInstruction(false, mnemonic);
805 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(op1);
806 if (!canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) {
807 return new UndefinedInstruction(machInst, false, mnemonic);
635 }
808 }
809 if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
810 Hstr, Hcptr, imm)) {
811 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP14_MCR_MRC);
812 }
636 Dest = MiscOp1;
637 '''
638
813 Dest = MiscOp1;
814 '''
815
639 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegOp",
816 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp",
640 { "code": mrc14code,
641 "predicate_test": predicateTest }, [])
817 { "code": mrc14code,
818 "predicate_test": predicateTest }, [])
642 header_output += RegRegOpDeclare.subst(mrc14Iop)
643 decoder_output += RegRegOpConstructor.subst(mrc14Iop)
819 header_output += RegRegImmOpDeclare.subst(mrc14Iop)
820 decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
644 exec_output += PredOpExecute.subst(mrc14Iop)
645
646
647 mcr14code = '''
821 exec_output += PredOpExecute.subst(mrc14Iop)
822
823
824 mcr14code = '''
648 CPSR cpsr = Cpsr;
649 if (cpsr.mode == MODE_USER) {
650 if (FullSystem)
651 return new UndefinedInstruction;
652 else
653 return new UndefinedInstruction(false, mnemonic);
825 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
826 if (!canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) {
827 return new UndefinedInstruction(machInst, false, mnemonic);
654 }
828 }
829 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
830 Hstr, Hcptr, imm)) {
831 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP14_MCR_MRC);
832 }
655 MiscDest = Op1;
656 '''
833 MiscDest = Op1;
834 '''
657 mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegOp",
835 mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp",
658 { "code": mcr14code,
659 "predicate_test": predicateTest },
660 ["IsSerializeAfter","IsNonSpeculative"])
836 { "code": mcr14code,
837 "predicate_test": predicateTest },
838 ["IsSerializeAfter","IsNonSpeculative"])
661 header_output += RegRegOpDeclare.subst(mcr14Iop)
662 decoder_output += RegRegOpConstructor.subst(mcr14Iop)
839 header_output += RegRegImmOpDeclare.subst(mcr14Iop)
840 decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
663 exec_output += PredOpExecute.subst(mcr14Iop)
664
841 exec_output += PredOpExecute.subst(mcr14Iop)
842
665 mrc14UserIop = InstObjParams("mrc", "Mrc14User", "RegRegOp",
666 { "code": "Dest = MiscOp1;",
667 "predicate_test": predicateTest }, [])
668 header_output += RegRegOpDeclare.subst(mrc14UserIop)
669 decoder_output += RegRegOpConstructor.subst(mrc14UserIop)
670 exec_output += PredOpExecute.subst(mrc14UserIop)
671
672 mcr14UserIop = InstObjParams("mcr", "Mcr14User", "RegRegOp",
673 { "code": "MiscDest = Op1",
674 "predicate_test": predicateTest },
675 ["IsSerializeAfter","IsNonSpeculative"])
676 header_output += RegRegOpDeclare.subst(mcr14UserIop)
677 decoder_output += RegRegOpConstructor.subst(mcr14UserIop)
678 exec_output += PredOpExecute.subst(mcr14UserIop)
679
680 mrc15code = '''
843 mrc15code = '''
681 CPSR cpsr = Cpsr;
682 if (cpsr.mode == MODE_USER) {
683 if (FullSystem)
684 return new UndefinedInstruction;
685 else
686 return new UndefinedInstruction(false, mnemonic);
844 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
845 MiscRegIndex miscReg = (MiscRegIndex)
846 xc->tcBase()->flattenMiscIndex(preFlatOp1);
847 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
848 Hcptr, imm);
849 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
850
851 // if we're in non secure PL1 mode then we can trap regargless of whether
852 // the register is accessable, in other modes we trap if only if the register
853 // IS accessable.
854 if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
855 return new UndefinedInstruction(machInst, false, mnemonic);
687 }
856 }
688 Dest = MiscOp1;
857 if (hypTrap) {
858 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC);
859 }
860 Dest = MiscNsBankedOp1;
689 '''
690
861 '''
862
691 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
863 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegImmOp",
692 { "code": mrc15code,
693 "predicate_test": predicateTest }, [])
864 { "code": mrc15code,
865 "predicate_test": predicateTest }, [])
694 header_output += RegRegOpDeclare.subst(mrc15Iop)
695 decoder_output += RegRegOpConstructor.subst(mrc15Iop)
866 header_output += RegRegImmOpDeclare.subst(mrc15Iop)
867 decoder_output += RegRegImmOpConstructor.subst(mrc15Iop)
696 exec_output += PredOpExecute.subst(mrc15Iop)
697
698
699 mcr15code = '''
868 exec_output += PredOpExecute.subst(mrc15Iop)
869
870
871 mcr15code = '''
700 CPSR cpsr = Cpsr;
701 if (cpsr.mode == MODE_USER) {
702 if (FullSystem)
703 return new UndefinedInstruction;
704 else
705 return new UndefinedInstruction(false, mnemonic);
872 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
873 MiscRegIndex miscReg = (MiscRegIndex)
874 xc->tcBase()->flattenMiscIndex(preFlatDest);
875 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
876 Hcptr, imm);
877 bool canWrite = canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
878
879 // if we're in non secure PL1 mode then we can trap regargless of whether
880 // the register is accessable, in other modes we trap if only if the register
881 // IS accessable.
882 if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
883 return new UndefinedInstruction(machInst, false, mnemonic);
706 }
884 }
707 MiscDest = Op1;
885 if (hypTrap) {
886 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC);
887 }
888 MiscNsBankedDest = Op1;
708 '''
889 '''
709 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
890 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegImmOp",
710 { "code": mcr15code,
711 "predicate_test": predicateTest },
712 ["IsSerializeAfter","IsNonSpeculative"])
891 { "code": mcr15code,
892 "predicate_test": predicateTest },
893 ["IsSerializeAfter","IsNonSpeculative"])
713 header_output += RegRegOpDeclare.subst(mcr15Iop)
714 decoder_output += RegRegOpConstructor.subst(mcr15Iop)
894 header_output += RegRegImmOpDeclare.subst(mcr15Iop)
895 decoder_output += RegRegImmOpConstructor.subst(mcr15Iop)
715 exec_output += PredOpExecute.subst(mcr15Iop)
716
896 exec_output += PredOpExecute.subst(mcr15Iop)
897
717 mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
718 { "code": "Dest = MiscOp1;",
719 "predicate_test": predicateTest }, [])
720 header_output += RegRegOpDeclare.subst(mrc15UserIop)
721 decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
722 exec_output += PredOpExecute.subst(mrc15UserIop)
723
898
724 mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
725 { "code": "MiscDest = Op1",
726 "predicate_test": predicateTest },
727 ["IsSerializeAfter","IsNonSpeculative"])
728 header_output += RegRegOpDeclare.subst(mcr15UserIop)
729 decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
730 exec_output += PredOpExecute.subst(mcr15UserIop)
899 mrrc15code = '''
900 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
901 MiscRegIndex miscReg = (MiscRegIndex)
902 xc->tcBase()->flattenMiscIndex(preFlatOp1);
903 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
904 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
731
905
906 // if we're in non secure PL1 mode then we can trap regargless of whether
907 // the register is accessable, in other modes we trap if only if the register
908 // IS accessable.
909 if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
910 return new UndefinedInstruction(machInst, false, mnemonic);
911 }
912 if (hypTrap) {
913 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC);
914 }
915 Dest = bits(MiscNsBankedOp164, 63, 32);
916 Dest2 = bits(MiscNsBankedOp164, 31, 0);
917 '''
918 mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp",
919 { "code": mrrc15code,
920 "predicate_test": predicateTest }, [])
921 header_output += MrrcOpDeclare.subst(mrrc15Iop)
922 decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
923 exec_output += PredOpExecute.subst(mrrc15Iop)
924
925
926 mcrr15code = '''
927 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
928 MiscRegIndex miscReg = (MiscRegIndex)
929 xc->tcBase()->flattenMiscIndex(preFlatDest);
930 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
931 bool canWrite = canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
932
933 // if we're in non secure PL1 mode then we can trap regargless of whether
934 // the register is accessable, in other modes we trap if only if the register
935 // IS accessable.
936 if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
937 return new UndefinedInstruction(machInst, false, mnemonic);
938 }
939 if (hypTrap) {
940 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC);
941 }
942 MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;
943 '''
944 mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp",
945 { "code": mcrr15code,
946 "predicate_test": predicateTest }, [])
947 header_output += McrrOpDeclare.subst(mcrr15Iop)
948 decoder_output += McrrOpConstructor.subst(mcrr15Iop)
949 exec_output += PredOpExecute.subst(mcrr15Iop)
950
951
732 enterxCode = '''
733 NextThumb = true;
734 NextJazelle = true;
735 '''
736 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
737 { "code": enterxCode,
738 "predicate_test": predicateTest }, [])
739 header_output += BasicDeclare.subst(enterxIop)

--- 30 unchanged lines hidden (view full) ---

770 clrexIop = InstObjParams("clrex", "Clrex","PredOp",
771 { "code": clrexCode,
772 "predicate_test": predicateTest },[])
773 header_output += BasicDeclare.subst(clrexIop)
774 decoder_output += BasicConstructor.subst(clrexIop)
775 exec_output += PredOpExecute.subst(clrexIop)
776
777 isbCode = '''
952 enterxCode = '''
953 NextThumb = true;
954 NextJazelle = true;
955 '''
956 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
957 { "code": enterxCode,
958 "predicate_test": predicateTest }, [])
959 header_output += BasicDeclare.subst(enterxIop)

--- 30 unchanged lines hidden (view full) ---

990 clrexIop = InstObjParams("clrex", "Clrex","PredOp",
991 { "code": clrexCode,
992 "predicate_test": predicateTest },[])
993 header_output += BasicDeclare.subst(clrexIop)
994 decoder_output += BasicConstructor.subst(clrexIop)
995 exec_output += PredOpExecute.subst(clrexIop)
996
997 isbCode = '''
998 // If the barrier is due to a CP15 access check for hyp traps
999 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr,
1000 Hdcr, Hstr, Hcptr, imm)) {
1001 return new HypervisorTrap(machInst, imm,
1002 EC_TRAPPED_CP15_MCR_MRC);
1003 }
778 fault = new FlushPipe;
779 '''
1004 fault = new FlushPipe;
1005 '''
780 isbIop = InstObjParams("isb", "Isb", "PredOp",
1006 isbIop = InstObjParams("isb", "Isb", "ImmOp",
781 {"code": isbCode,
782 "predicate_test": predicateTest},
783 ['IsSerializeAfter'])
1007 {"code": isbCode,
1008 "predicate_test": predicateTest},
1009 ['IsSerializeAfter'])
784 header_output += BasicDeclare.subst(isbIop)
785 decoder_output += BasicConstructor.subst(isbIop)
1010 header_output += ImmOpDeclare.subst(isbIop)
1011 decoder_output += ImmOpConstructor.subst(isbIop)
786 exec_output += PredOpExecute.subst(isbIop)
787
788 dsbCode = '''
1012 exec_output += PredOpExecute.subst(isbIop)
1013
1014 dsbCode = '''
1015 // If the barrier is due to a CP15 access check for hyp traps
1016 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr,
1017 Hdcr, Hstr, Hcptr, imm)) {
1018 return new HypervisorTrap(machInst, imm,
1019 EC_TRAPPED_CP15_MCR_MRC);
1020 }
789 fault = new FlushPipe;
790 '''
1021 fault = new FlushPipe;
1022 '''
791 dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
1023 dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
792 {"code": dsbCode,
793 "predicate_test": predicateTest},
794 ['IsMemBarrier', 'IsSerializeAfter'])
1024 {"code": dsbCode,
1025 "predicate_test": predicateTest},
1026 ['IsMemBarrier', 'IsSerializeAfter'])
795 header_output += BasicDeclare.subst(dsbIop)
796 decoder_output += BasicConstructor.subst(dsbIop)
1027 header_output += ImmOpDeclare.subst(dsbIop)
1028 decoder_output += ImmOpConstructor.subst(dsbIop)
797 exec_output += PredOpExecute.subst(dsbIop)
798
799 dmbCode = '''
1029 exec_output += PredOpExecute.subst(dsbIop)
1030
1031 dmbCode = '''
1032 // If the barrier is due to a CP15 access check for hyp traps
1033 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr,
1034 Hdcr, Hstr, Hcptr, imm)) {
1035 return new HypervisorTrap(machInst, imm,
1036 EC_TRAPPED_CP15_MCR_MRC);
1037 }
800 '''
1038 '''
801 dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
1039 dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
802 {"code": dmbCode,
803 "predicate_test": predicateTest},
804 ['IsMemBarrier'])
1040 {"code": dmbCode,
1041 "predicate_test": predicateTest},
1042 ['IsMemBarrier'])
805 header_output += BasicDeclare.subst(dmbIop)
806 decoder_output += BasicConstructor.subst(dmbIop)
1043 header_output += ImmOpDeclare.subst(dmbIop)
1044 decoder_output += ImmOpConstructor.subst(dmbIop)
807 exec_output += PredOpExecute.subst(dmbIop)
808
809 dbgCode = '''
810 '''
811 dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
812 {"code": dbgCode,
813 "predicate_test": predicateTest})
814 header_output += BasicDeclare.subst(dbgIop)

--- 36 unchanged lines hidden --- 		1045 exec_output += PredOpExecute.subst(dmbIop)
1046
1047 dbgCode = '''
1048 '''
1049 dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
1050 {"code": dbgCode,
1051 "predicate_test": predicateTest})
1052 header_output += BasicDeclare.subst(dbgIop)

--- 36 unchanged lines hidden ---