misc.isa (8782:10c9297e14d5) misc.isa (8796:a2ae5c378d0a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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44 fault = new SupervisorCall;
45 } else {
46 fault = new SupervisorCall(machInst);
47 }
48 '''
49
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
51 { "code": svcCode,
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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44 fault = new SupervisorCall;
45 } else {
46 fault = new SupervisorCall(machInst);
47 }
48 '''
49
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
51 { "code": svcCode,
52 "predicate_test": predicateTest }, ["IsSyscall"])
52 "predicate_test": predicateTest },
53 ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
53 header_output = BasicDeclare.subst(svcIop)
54 decoder_output = BasicConstructor.subst(svcIop)
55 exec_output = PredOpExecute.subst(svcIop)
56
57}};
58
59let {{
60

--- 736 unchanged lines hidden --- 		54 header_output = BasicDeclare.subst(svcIop)
55 decoder_output = BasicConstructor.subst(svcIop)
56 exec_output = PredOpExecute.subst(svcIop)
57
58}};
59
60let {{
61

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