misc.isa (8733:64a7bf8fa56c) misc.isa (8782:10c9297e14d5)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 svcCode = '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 svcCode = '''
43#if FULL_SYSTEM
44 fault = new SupervisorCall;
45#else
46 fault = new SupervisorCall(machInst);
47#endif
43 if (FullSystem) {
44 fault = new SupervisorCall;
45 } else {
46 fault = new SupervisorCall(machInst);
47 }
48 '''
49
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
51 { "code": svcCode,
48 '''
49
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
51 { "code": svcCode,
52 "predicate_test": predicateTest },
53 ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
52 "predicate_test": predicateTest }, ["IsSyscall"])
54 header_output = BasicDeclare.subst(svcIop)
55 decoder_output = BasicConstructor.subst(svcIop)
56 exec_output = PredOpExecute.subst(svcIop)
57
58}};
59
60let {{
61

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497
498 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
499 { "code" : "", "predicate_test" : predicateTest })
500 header_output += BasicDeclare.subst(yieldIop)
501 decoder_output += BasicConstructor.subst(yieldIop)
502 exec_output += PredOpExecute.subst(yieldIop)
503
504 wfeCode = '''
53 header_output = BasicDeclare.subst(svcIop)
54 decoder_output = BasicConstructor.subst(svcIop)
55 exec_output = PredOpExecute.subst(svcIop)
56
57}};
58
59let {{
60

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496
497 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
498 { "code" : "", "predicate_test" : predicateTest })
499 header_output += BasicDeclare.subst(yieldIop)
500 decoder_output += BasicConstructor.subst(yieldIop)
501 exec_output += PredOpExecute.subst(yieldIop)
502
503 wfeCode = '''
505#if FULL_SYSTEM
506 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
507 if (SevMailbox == 1) {
508 SevMailbox = 0;
509 PseudoInst::quiesceSkip(xc->tcBase());
510 } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) {
511 PseudoInst::quiesceSkip(xc->tcBase());
512 } else {
513 PseudoInst::quiesce(xc->tcBase());
514 }
504 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
505 if (SevMailbox == 1) {
506 SevMailbox = 0;
507 PseudoInst::quiesceSkip(xc->tcBase());
508 } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) {
509 PseudoInst::quiesceSkip(xc->tcBase());
510 } else {
511 PseudoInst::quiesce(xc->tcBase());
512 }
515#endif
516 '''
517 wfePredFixUpCode = '''
513 '''
514 wfePredFixUpCode = '''
518#if FULL_SYSTEM
519 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
520 // and SEV interrupts
521 SevMailbox = 1;
515 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
516 // and SEV interrupts
517 SevMailbox = 1;
522#endif
523 '''
524 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
525 { "code" : wfeCode,
526 "pred_fixup" : wfePredFixUpCode,
527 "predicate_test" : predicateTest },
518 '''
519 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
520 { "code" : wfeCode,
521 "pred_fixup" : wfePredFixUpCode,
522 "predicate_test" : predicateTest },
528 ["IsNonSpeculative", "IsQuiesce",
529 "IsSerializeAfter", "IsUnverifiable"])
523 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
530 header_output += BasicDeclare.subst(wfeIop)
531 decoder_output += BasicConstructor.subst(wfeIop)
532 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
533
534 wfiCode = '''
524 header_output += BasicDeclare.subst(wfeIop)
525 decoder_output += BasicConstructor.subst(wfeIop)
526 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
527
528 wfiCode = '''
535#if FULL_SYSTEM
536 // WFI doesn't sleep if interrupts are pending (masked or not)
537 if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
538 PseudoInst::quiesceSkip(xc->tcBase());
539 } else {
540 PseudoInst::quiesce(xc->tcBase());
541 }
529 // WFI doesn't sleep if interrupts are pending (masked or not)
530 if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
531 PseudoInst::quiesceSkip(xc->tcBase());
532 } else {
533 PseudoInst::quiesce(xc->tcBase());
534 }
542#endif
543 '''
544 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
545 { "code" : wfiCode, "predicate_test" : predicateTest },
535 '''
536 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
537 { "code" : wfiCode, "predicate_test" : predicateTest },
546 ["IsNonSpeculative", "IsQuiesce",
547 "IsSerializeAfter", "IsUnverifiable"])
538 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
548 header_output += BasicDeclare.subst(wfiIop)
549 decoder_output += BasicConstructor.subst(wfiIop)
550 exec_output += QuiescePredOpExecute.subst(wfiIop)
551
552 sevCode = '''
539 header_output += BasicDeclare.subst(wfiIop)
540 decoder_output += BasicConstructor.subst(wfiIop)
541 exec_output += QuiescePredOpExecute.subst(wfiIop)
542
543 sevCode = '''
553#if FULL_SYSTEM
554 SevMailbox = 1;
555 System *sys = xc->tcBase()->getSystemPtr();
556 for (int x = 0; x < sys->numContexts(); x++) {
557 ThreadContext *oc = sys->getThreadContext(x);
558 if (oc == xc->tcBase())
559 continue;
560 // Wake CPU with interrupt if they were sleeping
561 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
562 // Post Interrupt and wake cpu if needed
563 oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
564 }
565 }
544 SevMailbox = 1;
545 System *sys = xc->tcBase()->getSystemPtr();
546 for (int x = 0; x < sys->numContexts(); x++) {
547 ThreadContext *oc = sys->getThreadContext(x);
548 if (oc == xc->tcBase())
549 continue;
550 // Wake CPU with interrupt if they were sleeping
551 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
552 // Post Interrupt and wake cpu if needed
553 oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
554 }
555 }
566#endif
567 '''
568 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
569 { "code" : sevCode, "predicate_test" : predicateTest },
556 '''
557 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
558 { "code" : sevCode, "predicate_test" : predicateTest },
570 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
559 ["IsNonSpeculative", "IsSquashAfter"])
571 header_output += BasicDeclare.subst(sevIop)
572 decoder_output += BasicConstructor.subst(sevIop)
573 exec_output += PredOpExecute.subst(sevIop)
574
575 itIop = InstObjParams("it", "ItInst", "PredOp", \
576 { "code" : ";",
577 "predicate_test" : predicateTest },
578 ["IsNonSpeculative", "IsSerializeAfter"])
579 header_output += BasicDeclare.subst(itIop)
580 decoder_output += BasicConstructor.subst(itIop)
581 exec_output += PredOpExecute.subst(itIop)
582 unknownCode = '''
560 header_output += BasicDeclare.subst(sevIop)
561 decoder_output += BasicConstructor.subst(sevIop)
562 exec_output += PredOpExecute.subst(sevIop)
563
564 itIop = InstObjParams("it", "ItInst", "PredOp", \
565 { "code" : ";",
566 "predicate_test" : predicateTest },
567 ["IsNonSpeculative", "IsSerializeAfter"])
568 header_output += BasicDeclare.subst(itIop)
569 decoder_output += BasicConstructor.subst(itIop)
570 exec_output += PredOpExecute.subst(itIop)
571 unknownCode = '''
583#if FULL_SYSTEM
584 return new UndefinedInstruction;
585#else
586 return new UndefinedInstruction(machInst, true);
587#endif
572 if (FullSystem)
573 return new UndefinedInstruction;
574 else
575 return new UndefinedInstruction(machInst, true);
588 '''
589 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
590 { "code": unknownCode,
591 "predicate_test": predicateTest })
592 header_output += BasicDeclare.subst(unknownIop)
593 decoder_output += BasicConstructor.subst(unknownIop)
594 exec_output += PredOpExecute.subst(unknownIop)
595

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632 { "code": bfiCode,
633 "predicate_test": predicateTest }, [])
634 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
635 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
636 exec_output += PredOpExecute.subst(bfiIop)
637
638 mrc15code = '''
639 CPSR cpsr = Cpsr;
576 '''
577 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
578 { "code": unknownCode,
579 "predicate_test": predicateTest })
580 header_output += BasicDeclare.subst(unknownIop)
581 decoder_output += BasicConstructor.subst(unknownIop)
582 exec_output += PredOpExecute.subst(unknownIop)
583

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620 { "code": bfiCode,
621 "predicate_test": predicateTest }, [])
622 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
623 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
624 exec_output += PredOpExecute.subst(bfiIop)
625
626 mrc15code = '''
627 CPSR cpsr = Cpsr;
640 if (cpsr.mode == MODE_USER)
641#if FULL_SYSTEM
642 return new UndefinedInstruction;
643#else
644 return new UndefinedInstruction(false, mnemonic);
645#endif
628 if (cpsr.mode == MODE_USER) {
629 if (FullSystem)
630 return new UndefinedInstruction;
631 else
632 return new UndefinedInstruction(false, mnemonic);
633 }
646 Dest = MiscOp1;
647 '''
648
649 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
650 { "code": mrc15code,
651 "predicate_test": predicateTest }, [])
652 header_output += RegRegOpDeclare.subst(mrc15Iop)
653 decoder_output += RegRegOpConstructor.subst(mrc15Iop)
654 exec_output += PredOpExecute.subst(mrc15Iop)
655
656
657 mcr15code = '''
658 CPSR cpsr = Cpsr;
634 Dest = MiscOp1;
635 '''
636
637 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
638 { "code": mrc15code,
639 "predicate_test": predicateTest }, [])
640 header_output += RegRegOpDeclare.subst(mrc15Iop)
641 decoder_output += RegRegOpConstructor.subst(mrc15Iop)
642 exec_output += PredOpExecute.subst(mrc15Iop)
643
644
645 mcr15code = '''
646 CPSR cpsr = Cpsr;
659 if (cpsr.mode == MODE_USER)
660#if FULL_SYSTEM
661 return new UndefinedInstruction;
662#else
663 return new UndefinedInstruction(false, mnemonic);
664#endif
647 if (cpsr.mode == MODE_USER) {
648 if (FullSystem)
649 return new UndefinedInstruction;
650 else
651 return new UndefinedInstruction(false, mnemonic);
652 }
665 MiscDest = Op1;
666 '''
667 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
668 { "code": mcr15code,
669 "predicate_test": predicateTest },
670 ["IsSerializeAfter","IsNonSpeculative"])
671 header_output += RegRegOpDeclare.subst(mcr15Iop)
672 decoder_output += RegRegOpConstructor.subst(mcr15Iop)

--- 136 unchanged lines hidden --- 		653 MiscDest = Op1;
654 '''
655 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
656 { "code": mcr15code,
657 "predicate_test": predicateTest },
658 ["IsSerializeAfter","IsNonSpeculative"])
659 header_output += RegRegOpDeclare.subst(mcr15Iop)
660 decoder_output += RegRegOpConstructor.subst(mcr15Iop)

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