| misc.isa (8518:9c87727099ce) | misc.isa (8588:ef28ed90449d) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 273 unchanged lines hidden (view full) --- 282 { "code": usat16Code, 283 "predicate_test": pickPredicate(usat16Code) }, []) 284 header_output += RegImmRegOpDeclare.subst(usat16Iop) 285 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 286 exec_output += PredOpExecute.subst(usat16Iop) 287 288 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 289 { "code": | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 273 unchanged lines hidden (view full) --- 282 { "code": usat16Code, 283 "predicate_test": pickPredicate(usat16Code) }, []) 284 header_output += RegImmRegOpDeclare.subst(usat16Iop) 285 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 286 exec_output += PredOpExecute.subst(usat16Iop) 287 288 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 289 { "code": |
| 290 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));", | 290 "Dest = sext<8>((uint8_t)(Op1_ud >> imm));", |
| 291 "predicate_test": predicateTest }, []) 292 header_output += RegImmRegOpDeclare.subst(sxtbIop) 293 decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 294 exec_output += PredOpExecute.subst(sxtbIop) 295 296 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 297 { "code": 298 ''' | 291 "predicate_test": predicateTest }, []) 292 header_output += RegImmRegOpDeclare.subst(sxtbIop) 293 decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 294 exec_output += PredOpExecute.subst(sxtbIop) 295 296 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 297 { "code": 298 ''' |
| 299 Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + | 299 Dest = sext<8>((uint8_t)(Op2_ud >> imm)) + |
| 300 Op1; 301 ''', 302 "predicate_test": predicateTest }, []) 303 header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 304 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 305 exec_output += PredOpExecute.subst(sxtabIop) 306 307 sxtb16Code = ''' --- 46 unchanged lines hidden (view full) --- 354 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 355 { "code": sxtahCode, 356 "predicate_test": predicateTest }, []) 357 header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 358 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 359 exec_output += PredOpExecute.subst(sxtahIop) 360 361 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", | 300 Op1; 301 ''', 302 "predicate_test": predicateTest }, []) 303 header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 304 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 305 exec_output += PredOpExecute.subst(sxtabIop) 306 307 sxtb16Code = ''' --- 46 unchanged lines hidden (view full) --- 354 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 355 { "code": sxtahCode, 356 "predicate_test": predicateTest }, []) 357 header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 358 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 359 exec_output += PredOpExecute.subst(sxtahIop) 360 361 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", |
| 362 { "code": "Dest = (uint8_t)(Op1.ud >> imm);", | 362 { "code": "Dest = (uint8_t)(Op1_ud >> imm);", |
| 363 "predicate_test": predicateTest }, []) 364 header_output += RegImmRegOpDeclare.subst(uxtbIop) 365 decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 366 exec_output += PredOpExecute.subst(uxtbIop) 367 368 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 369 { "code": | 363 "predicate_test": predicateTest }, []) 364 header_output += RegImmRegOpDeclare.subst(uxtbIop) 365 decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 366 exec_output += PredOpExecute.subst(uxtbIop) 367 368 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 369 { "code": |
| 370 "Dest = (uint8_t)(Op2.ud >> imm) + Op1;", | 370 "Dest = (uint8_t)(Op2_ud >> imm) + Op1;", |
| 371 "predicate_test": predicateTest }, []) 372 header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 373 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 374 exec_output += PredOpExecute.subst(uxtabIop) 375 376 uxtb16Code = ''' 377 uint32_t resTemp = 0; 378 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); --- 427 unchanged lines hidden --- | 371 "predicate_test": predicateTest }, []) 372 header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 373 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 374 exec_output += PredOpExecute.subst(uxtabIop) 375 376 uxtb16Code = ''' 377 uint32_t resTemp = 0; 378 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); --- 427 unchanged lines hidden --- |