misc.isa (8303:5a95f1d2494e) misc.isa (8304:16911ff780d3)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 212 unchanged lines hidden (view full) ---

221 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
222 int32_t res;
223 if (satInt(res, operand, imm))
224 CpsrQ = 1 << 27;
225 Dest = res;
226 '''
227 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
228 { "code": ssatCode,
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 212 unchanged lines hidden (view full) ---

221 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
222 int32_t res;
223 if (satInt(res, operand, imm))
224 CpsrQ = 1 << 27;
225 Dest = res;
226 '''
227 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
228 { "code": ssatCode,
229 "predicate_test": condPredicateTest }, [])
229 "predicate_test": pickPredicate(ssatCode) }, [])
230 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
231 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
232 exec_output += PredOpExecute.subst(ssatIop)
233
234 usatCode = '''
235 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
236 int32_t res;
237 if (uSatInt(res, operand, imm))
238 CpsrQ = 1 << 27;
239 Dest = res;
240 '''
241 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
242 { "code": usatCode,
230 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
231 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
232 exec_output += PredOpExecute.subst(ssatIop)
233
234 usatCode = '''
235 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
236 int32_t res;
237 if (uSatInt(res, operand, imm))
238 CpsrQ = 1 << 27;
239 Dest = res;
240 '''
241 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
242 { "code": usatCode,
243 "predicate_test": condPredicateTest }, [])
243 "predicate_test": pickPredicate(usatCode) }, [])
244 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
245 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
246 exec_output += PredOpExecute.subst(usatIop)
247
248 ssat16Code = '''
249 int32_t res;
250 uint32_t resTemp = 0;
251 int32_t argLow = sext<16>(bits(Op1, 15, 0));
252 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
253 if (satInt(res, argLow, imm))
254 CpsrQ = 1 << 27;
255 replaceBits(resTemp, 15, 0, res);
256 if (satInt(res, argHigh, imm))
257 CpsrQ = 1 << 27;
258 replaceBits(resTemp, 31, 16, res);
259 Dest = resTemp;
260 '''
261 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
262 { "code": ssat16Code,
244 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
245 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
246 exec_output += PredOpExecute.subst(usatIop)
247
248 ssat16Code = '''
249 int32_t res;
250 uint32_t resTemp = 0;
251 int32_t argLow = sext<16>(bits(Op1, 15, 0));
252 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
253 if (satInt(res, argLow, imm))
254 CpsrQ = 1 << 27;
255 replaceBits(resTemp, 15, 0, res);
256 if (satInt(res, argHigh, imm))
257 CpsrQ = 1 << 27;
258 replaceBits(resTemp, 31, 16, res);
259 Dest = resTemp;
260 '''
261 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
262 { "code": ssat16Code,
263 "predicate_test": condPredicateTest }, [])
263 "predicate_test": pickPredicate(ssat16Code) }, [])
264 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
265 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
266 exec_output += PredOpExecute.subst(ssat16Iop)
267
268 usat16Code = '''
269 int32_t res;
270 uint32_t resTemp = 0;
271 int32_t argLow = sext<16>(bits(Op1, 15, 0));
272 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
273 if (uSatInt(res, argLow, imm))
274 CpsrQ = 1 << 27;
275 replaceBits(resTemp, 15, 0, res);
276 if (uSatInt(res, argHigh, imm))
277 CpsrQ = 1 << 27;
278 replaceBits(resTemp, 31, 16, res);
279 Dest = resTemp;
280 '''
281 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
282 { "code": usat16Code,
264 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
265 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
266 exec_output += PredOpExecute.subst(ssat16Iop)
267
268 usat16Code = '''
269 int32_t res;
270 uint32_t resTemp = 0;
271 int32_t argLow = sext<16>(bits(Op1, 15, 0));
272 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
273 if (uSatInt(res, argLow, imm))
274 CpsrQ = 1 << 27;
275 replaceBits(resTemp, 15, 0, res);
276 if (uSatInt(res, argHigh, imm))
277 CpsrQ = 1 << 27;
278 replaceBits(resTemp, 31, 16, res);
279 Dest = resTemp;
280 '''
281 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
282 { "code": usat16Code,
283 "predicate_test": condPredicateTest }, [])
283 "predicate_test": pickPredicate(usat16Code) }, [])
284 header_output += RegImmRegOpDeclare.subst(usat16Iop)
285 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
286 exec_output += PredOpExecute.subst(usat16Iop)
287
288 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
289 { "code":
290 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
291 "predicate_test": predicateTest }, [])

--- 501 unchanged lines hidden --- 		284 header_output += RegImmRegOpDeclare.subst(usat16Iop)
285 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
286 exec_output += PredOpExecute.subst(usat16Iop)
287
288 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
289 { "code":
290 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
291 "predicate_test": predicateTest }, [])

--- 501 unchanged lines hidden ---