misc.isa (8209:9e3f7f00fa90) misc.isa (8285:c38905a6fa32)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 469 unchanged lines hidden (view full) ---

478 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
479 { "code" : "", "predicate_test" : predicateTest })
480 header_output += BasicDeclare.subst(yieldIop)
481 decoder_output += BasicConstructor.subst(yieldIop)
482 exec_output += PredOpExecute.subst(yieldIop)
483
484 wfeCode = '''
485#if FULL_SYSTEM
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 469 unchanged lines hidden (view full) ---

478 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
479 { "code" : "", "predicate_test" : predicateTest })
480 header_output += BasicDeclare.subst(yieldIop)
481 decoder_output += BasicConstructor.subst(yieldIop)
482 exec_output += PredOpExecute.subst(yieldIop)
483
484 wfeCode = '''
485#if FULL_SYSTEM
486 if (SevMailbox) {
486 if (SevMailbox == 1) {
487 SevMailbox = 0;
488 PseudoInst::quiesceSkip(xc->tcBase());
487 SevMailbox = 0;
488 PseudoInst::quiesceSkip(xc->tcBase());
489 }
490 else {
489 } else {
491 PseudoInst::quiesce(xc->tcBase());
492 }
493#endif
494 '''
495 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
496 { "code" : wfeCode, "predicate_test" : predicateTest },
497 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
498 header_output += BasicDeclare.subst(wfeIop)
499 decoder_output += BasicConstructor.subst(wfeIop)
500 exec_output += QuiescePredOpExecute.subst(wfeIop)
501
502 wfiCode = '''
503#if FULL_SYSTEM
490 PseudoInst::quiesce(xc->tcBase());
491 }
492#endif
493 '''
494 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
495 { "code" : wfeCode, "predicate_test" : predicateTest },
496 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
497 header_output += BasicDeclare.subst(wfeIop)
498 decoder_output += BasicConstructor.subst(wfeIop)
499 exec_output += QuiescePredOpExecute.subst(wfeIop)
500
501 wfiCode = '''
502#if FULL_SYSTEM
504 PseudoInst::quiesce(xc->tcBase());
503 // WFI doesn't sleep if interrupts are pending (masked or not)
504 if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
505 PseudoInst::quiesceSkip(xc->tcBase());
506 } else {
507 PseudoInst::quiesce(xc->tcBase());
508 }
505#endif
506 '''
507 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
508 { "code" : wfiCode, "predicate_test" : predicateTest },
509 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
510 header_output += BasicDeclare.subst(wfiIop)
511 decoder_output += BasicConstructor.subst(wfiIop)
512 exec_output += QuiescePredOpExecute.subst(wfiIop)
513
514 sevCode = '''
515 // Need a way for O3 to not scoreboard these accesses as pipe flushes.
516 SevMailbox = 1;
517 System *sys = xc->tcBase()->getSystemPtr();
518 for (int x = 0; x < sys->numContexts(); x++) {
519 ThreadContext *oc = sys->getThreadContext(x);
509#endif
510 '''
511 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
512 { "code" : wfiCode, "predicate_test" : predicateTest },
513 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
514 header_output += BasicDeclare.subst(wfiIop)
515 decoder_output += BasicConstructor.subst(wfiIop)
516 exec_output += QuiescePredOpExecute.subst(wfiIop)
517
518 sevCode = '''
519 // Need a way for O3 to not scoreboard these accesses as pipe flushes.
520 SevMailbox = 1;
521 System *sys = xc->tcBase()->getSystemPtr();
522 for (int x = 0; x < sys->numContexts(); x++) {
523 ThreadContext *oc = sys->getThreadContext(x);
520 if (oc != xc->tcBase()) {
524 if (oc == xc->tcBase())
525 continue;
526 // Only wake if they were sleeping
527 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
521 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
528 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
529 PseudoInst::wakeCPU(xc->tcBase(), x);
522 }
523 }
524 '''
525 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
526 { "code" : sevCode, "predicate_test" : predicateTest },
527 ["IsNonSpeculative", "IsSquashAfter"])
528 header_output += BasicDeclare.subst(sevIop)
529 decoder_output += BasicConstructor.subst(sevIop)

--- 236 unchanged lines hidden --- 		530 }
531 }
532 '''
533 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
534 { "code" : sevCode, "predicate_test" : predicateTest },
535 ["IsNonSpeculative", "IsSquashAfter"])
536 header_output += BasicDeclare.subst(sevIop)
537 decoder_output += BasicConstructor.subst(sevIop)

--- 236 unchanged lines hidden ---