misc.isa (8142:e08035e1a1f6) misc.isa (8205:7ecbffb674aa)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 69 unchanged lines hidden (view full) ---

78 decoder_output += MrsConstructor.subst(mrsSpsrIop)
79 exec_output += PredOpExecute.subst(mrsSpsrIop)
80
81 msrCpsrRegCode = '''
82 SCTLR sctlr = Sctlr;
83 uint32_t newCpsr =
84 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
85 Cpsr = ~CondCodesMask & newCpsr;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 69 unchanged lines hidden (view full) ---

78 decoder_output += MrsConstructor.subst(mrsSpsrIop)
79 exec_output += PredOpExecute.subst(mrsSpsrIop)
80
81 msrCpsrRegCode = '''
82 SCTLR sctlr = Sctlr;
83 uint32_t newCpsr =
84 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
85 Cpsr = ~CondCodesMask & newCpsr;
86 NextThumb = ((CPSR)newCpsr).t;
87 NextJazelle = ((CPSR)newCpsr).j;
88 ForcedItState = ((((CPSR)Op1).it2 << 2) & 0xFC)
89 | (((CPSR)Op1).it1 & 0x3);
90 CondCodes = CondCodesMask & newCpsr;
91 '''
92 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
93 { "code": msrCpsrRegCode,
94 "predicate_test": condPredicateTest },
95 ["IsSerializeAfter","IsNonSpeculative"])
96 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
97 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)

--- 8 unchanged lines hidden (view full) ---

106 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
107 exec_output += PredOpExecute.subst(msrSpsrRegIop)
108
109 msrCpsrImmCode = '''
110 SCTLR sctlr = Sctlr;
111 uint32_t newCpsr =
112 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
113 Cpsr = ~CondCodesMask & newCpsr;
86 CondCodes = CondCodesMask & newCpsr;
87 '''
88 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
89 { "code": msrCpsrRegCode,
90 "predicate_test": condPredicateTest },
91 ["IsSerializeAfter","IsNonSpeculative"])
92 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
93 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)

--- 8 unchanged lines hidden (view full) ---

102 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
103 exec_output += PredOpExecute.subst(msrSpsrRegIop)
104
105 msrCpsrImmCode = '''
106 SCTLR sctlr = Sctlr;
107 uint32_t newCpsr =
108 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
109 Cpsr = ~CondCodesMask & newCpsr;
114 NextThumb = ((CPSR)newCpsr).t;
115 NextJazelle = ((CPSR)newCpsr).j;
116 ForcedItState = ((((CPSR)imm).it2 << 2) & 0xFC)
117 | (((CPSR)imm).it1 & 0x3);
118 CondCodes = CondCodesMask & newCpsr;
119 '''
120 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
121 { "code": msrCpsrImmCode,
122 "predicate_test": condPredicateTest },
123 ["IsSerializeAfter","IsNonSpeculative"])
124 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
125 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)

--- 407 unchanged lines hidden (view full) ---

533 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
534 { "code" : sevCode, "predicate_test" : predicateTest },
535 ["IsNonSpeculative", "IsSquashAfter"])
536 header_output += BasicDeclare.subst(sevIop)
537 decoder_output += BasicConstructor.subst(sevIop)
538 exec_output += PredOpExecute.subst(sevIop)
539
540 itIop = InstObjParams("it", "ItInst", "PredOp", \
110 CondCodes = CondCodesMask & newCpsr;
111 '''
112 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
113 { "code": msrCpsrImmCode,
114 "predicate_test": condPredicateTest },
115 ["IsSerializeAfter","IsNonSpeculative"])
116 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
117 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)

--- 407 unchanged lines hidden (view full) ---

525 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
526 { "code" : sevCode, "predicate_test" : predicateTest },
527 ["IsNonSpeculative", "IsSquashAfter"])
528 header_output += BasicDeclare.subst(sevIop)
529 decoder_output += BasicConstructor.subst(sevIop)
530 exec_output += PredOpExecute.subst(sevIop)
531
532 itIop = InstObjParams("it", "ItInst", "PredOp", \
541 { "code" : "Itstate = machInst.newItstate;",
533 { "code" : ";",
542 "predicate_test" : predicateTest },
543 ["IsNonSpeculative", "IsSerializeAfter"])
544 header_output += BasicDeclare.subst(itIop)
545 decoder_output += BasicConstructor.subst(itIop)
546 exec_output += PredOpExecute.subst(itIop)
547 unknownCode = '''
548#if FULL_SYSTEM
549 return new UndefinedInstruction;

--- 228 unchanged lines hidden --- 		534 "predicate_test" : predicateTest },
535 ["IsNonSpeculative", "IsSerializeAfter"])
536 header_output += BasicDeclare.subst(itIop)
537 decoder_output += BasicConstructor.subst(itIop)
538 exec_output += PredOpExecute.subst(itIop)
539 unknownCode = '''
540#if FULL_SYSTEM
541 return new UndefinedInstruction;

--- 228 unchanged lines hidden ---