misc.isa (7783:9b880b40ac10) misc.isa (7797:998b217dcae7)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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78 decoder_output += MrsConstructor.subst(mrsSpsrIop)
79 exec_output += PredOpExecute.subst(mrsSpsrIop)
80
81 msrCpsrRegCode = '''
82 SCTLR sctlr = Sctlr;
83 uint32_t newCpsr =
84 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
85 Cpsr = ~CondCodesMask & newCpsr;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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78 decoder_output += MrsConstructor.subst(mrsSpsrIop)
79 exec_output += PredOpExecute.subst(mrsSpsrIop)
80
81 msrCpsrRegCode = '''
82 SCTLR sctlr = Sctlr;
83 uint32_t newCpsr =
84 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
85 Cpsr = ~CondCodesMask & newCpsr;
86 ArmISA::PCState pc = PCS;
87 pc.nextThumb(((CPSR)newCpsr).t);
88 pc.nextJazelle(((CPSR)newCpsr).j);
89 PCS = pc;
86 NextThumb = ((CPSR)newCpsr).t;
87 NextJazelle = ((CPSR)newCpsr).j;
90 CondCodes = CondCodesMask & newCpsr;
91 '''
92 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
93 { "code": msrCpsrRegCode,
94 "predicate_test": condPredicateTest },
95 ["IsSerializeAfter","IsNonSpeculative"])
96 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
97 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)

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106 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
107 exec_output += PredOpExecute.subst(msrSpsrRegIop)
108
109 msrCpsrImmCode = '''
110 SCTLR sctlr = Sctlr;
111 uint32_t newCpsr =
112 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
113 Cpsr = ~CondCodesMask & newCpsr;
88 CondCodes = CondCodesMask & newCpsr;
89 '''
90 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
91 { "code": msrCpsrRegCode,
92 "predicate_test": condPredicateTest },
93 ["IsSerializeAfter","IsNonSpeculative"])
94 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
95 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)

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104 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
105 exec_output += PredOpExecute.subst(msrSpsrRegIop)
106
107 msrCpsrImmCode = '''
108 SCTLR sctlr = Sctlr;
109 uint32_t newCpsr =
110 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
111 Cpsr = ~CondCodesMask & newCpsr;
114 ArmISA::PCState pc = PCS;
115 pc.nextThumb(((CPSR)newCpsr).t);
116 pc.nextJazelle(((CPSR)newCpsr).j);
117 PCS = pc;
112 NextThumb = ((CPSR)newCpsr).t;
113 NextJazelle = ((CPSR)newCpsr).j;
118 CondCodes = CondCodesMask & newCpsr;
119 '''
120 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
121 { "code": msrCpsrImmCode,
122 "predicate_test": condPredicateTest },
123 ["IsSerializeAfter","IsNonSpeculative"])
124 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
125 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)

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465 '''
466 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
467 { "code": usada8Code,
468 "predicate_test": predicateTest }, [])
469 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
470 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
471 exec_output += PredOpExecute.subst(usada8Iop)
472
114 CondCodes = CondCodesMask & newCpsr;
115 '''
116 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
117 { "code": msrCpsrImmCode,
118 "predicate_test": condPredicateTest },
119 ["IsSerializeAfter","IsNonSpeculative"])
120 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
121 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)

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461 '''
462 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
463 { "code": usada8Code,
464 "predicate_test": predicateTest }, [])
465 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
466 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
467 exec_output += PredOpExecute.subst(usada8Iop)
468
473 bkptCode = '''
474 ArmISA::PCState pc = PCS;
475 return new PrefetchAbort(pc.pc(), ArmFault::DebugEvent);
476 '''
469 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
477 bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
478 bkptCode)
479 header_output += BasicDeclare.subst(bkptIop)
480 decoder_output += BasicConstructor.subst(bkptIop)
481 exec_output += BasicExecute.subst(bkptIop)
482
483 nopIop = InstObjParams("nop", "NopInst", "PredOp", \
484 { "code" : "", "predicate_test" : predicateTest })

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645 { "code": "MiscDest = Op1",
646 "predicate_test": predicateTest },
647 ["IsSerializeAfter","IsNonSpeculative"])
648 header_output += RegRegOpDeclare.subst(mcr15UserIop)
649 decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
650 exec_output += PredOpExecute.subst(mcr15UserIop)
651
652 enterxCode = '''
470 bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
471 bkptCode)
472 header_output += BasicDeclare.subst(bkptIop)
473 decoder_output += BasicConstructor.subst(bkptIop)
474 exec_output += BasicExecute.subst(bkptIop)
475
476 nopIop = InstObjParams("nop", "NopInst", "PredOp", \
477 { "code" : "", "predicate_test" : predicateTest })

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638 { "code": "MiscDest = Op1",
639 "predicate_test": predicateTest },
640 ["IsSerializeAfter","IsNonSpeculative"])
641 header_output += RegRegOpDeclare.subst(mcr15UserIop)
642 decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
643 exec_output += PredOpExecute.subst(mcr15UserIop)
644
645 enterxCode = '''
653 ArmISA::PCState pc = PCS;
654 pc.nextThumb(true);
655 pc.nextJazelle(true);
656 PCS = pc;
646 NextThumb = true;
647 NextJazelle = true;
657 '''
658 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
659 { "code": enterxCode,
660 "predicate_test": predicateTest }, [])
661 header_output += BasicDeclare.subst(enterxIop)
662 decoder_output += BasicConstructor.subst(enterxIop)
663 exec_output += PredOpExecute.subst(enterxIop)
664
665 leavexCode = '''
648 '''
649 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
650 { "code": enterxCode,
651 "predicate_test": predicateTest }, [])
652 header_output += BasicDeclare.subst(enterxIop)
653 decoder_output += BasicConstructor.subst(enterxIop)
654 exec_output += PredOpExecute.subst(enterxIop)
655
656 leavexCode = '''
666 ArmISA::PCState pc = PCS;
667 pc.nextThumb(true);
668 pc.nextJazelle(false);
669 PCS = pc;
657 NextThumb = true;
658 NextJazelle = false;
670 '''
671 leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
672 { "code": leavexCode,
673 "predicate_test": predicateTest }, [])
674 header_output += BasicDeclare.subst(leavexIop)
675 decoder_output += BasicConstructor.subst(leavexIop)
676 exec_output += PredOpExecute.subst(leavexIop)
677

--- 96 unchanged lines hidden --- 		659 '''
660 leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
661 { "code": leavexCode,
662 "predicate_test": predicateTest }, [])
663 header_output += BasicDeclare.subst(leavexIop)
664 decoder_output += BasicConstructor.subst(leavexIop)
665 exec_output += PredOpExecute.subst(leavexIop)
666

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