misc.isa (7705:fd65f85fcc0c) misc.isa (7720:65d338a8dba4)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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78 decoder_output += MrsConstructor.subst(mrsSpsrIop)
79 exec_output += PredOpExecute.subst(mrsSpsrIop)
80
81 msrCpsrRegCode = '''
82 SCTLR sctlr = Sctlr;
83 uint32_t newCpsr =
84 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
85 Cpsr = ~CondCodesMask & newCpsr;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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78 decoder_output += MrsConstructor.subst(mrsSpsrIop)
79 exec_output += PredOpExecute.subst(mrsSpsrIop)
80
81 msrCpsrRegCode = '''
82 SCTLR sctlr = Sctlr;
83 uint32_t newCpsr =
84 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
85 Cpsr = ~CondCodesMask & newCpsr;
86 ArmISA::PCState pc = PCS;
87 pc.nextThumb(((CPSR)newCpsr).t);
88 pc.nextJazelle(((CPSR)newCpsr).j);
89 PCS = pc;
86 CondCodes = CondCodesMask & newCpsr;
87 '''
88 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
89 { "code": msrCpsrRegCode,
90 "predicate_test": condPredicateTest },
91 ["IsSerializeAfter","IsNonSpeculative"])
92 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
93 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)

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102 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
103 exec_output += PredOpExecute.subst(msrSpsrRegIop)
104
105 msrCpsrImmCode = '''
106 SCTLR sctlr = Sctlr;
107 uint32_t newCpsr =
108 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
109 Cpsr = ~CondCodesMask & newCpsr;
90 CondCodes = CondCodesMask & newCpsr;
91 '''
92 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
93 { "code": msrCpsrRegCode,
94 "predicate_test": condPredicateTest },
95 ["IsSerializeAfter","IsNonSpeculative"])
96 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
97 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)

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106 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
107 exec_output += PredOpExecute.subst(msrSpsrRegIop)
108
109 msrCpsrImmCode = '''
110 SCTLR sctlr = Sctlr;
111 uint32_t newCpsr =
112 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
113 Cpsr = ~CondCodesMask & newCpsr;
114 ArmISA::PCState pc = PCS;
115 pc.nextThumb(((CPSR)newCpsr).t);
116 pc.nextJazelle(((CPSR)newCpsr).j);
117 PCS = pc;
110 CondCodes = CondCodesMask & newCpsr;
111 '''
112 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
113 { "code": msrCpsrImmCode,
114 "predicate_test": condPredicateTest },
115 ["IsSerializeAfter","IsNonSpeculative"])
116 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
117 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)

--- 339 unchanged lines hidden (view full) ---

457 '''
458 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
459 { "code": usada8Code,
460 "predicate_test": predicateTest }, [])
461 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
462 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
463 exec_output += PredOpExecute.subst(usada8Iop)
464
118 CondCodes = CondCodesMask & newCpsr;
119 '''
120 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
121 { "code": msrCpsrImmCode,
122 "predicate_test": condPredicateTest },
123 ["IsSerializeAfter","IsNonSpeculative"])
124 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
125 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)

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465 '''
466 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
467 { "code": usada8Code,
468 "predicate_test": predicateTest }, [])
469 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
470 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
471 exec_output += PredOpExecute.subst(usada8Iop)
472
473 bkptCode = '''
474 ArmISA::PCState pc = PCS;
475 return new PrefetchAbort(pc.pc(), ArmFault::DebugEvent);
476 '''
465 bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
477 bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
466 "return new PrefetchAbort(PC, ArmFault::DebugEvent);")
478 bkptCode)
467 header_output += BasicDeclare.subst(bkptIop)
468 decoder_output += BasicConstructor.subst(bkptIop)
469 exec_output += BasicExecute.subst(bkptIop)
470
471 nopIop = InstObjParams("nop", "NopInst", "PredOp", \
472 { "code" : "", "predicate_test" : predicateTest })
473 header_output += BasicDeclare.subst(nopIop)
474 decoder_output += BasicConstructor.subst(nopIop)

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633 { "code": "MiscDest = Op1",
634 "predicate_test": predicateTest },
635 ["IsSerializeAfter","IsNonSpeculative"])
636 header_output += RegRegOpDeclare.subst(mcr15UserIop)
637 decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
638 exec_output += PredOpExecute.subst(mcr15UserIop)
639
640 enterxCode = '''
479 header_output += BasicDeclare.subst(bkptIop)
480 decoder_output += BasicConstructor.subst(bkptIop)
481 exec_output += BasicExecute.subst(bkptIop)
482
483 nopIop = InstObjParams("nop", "NopInst", "PredOp", \
484 { "code" : "", "predicate_test" : predicateTest })
485 header_output += BasicDeclare.subst(nopIop)
486 decoder_output += BasicConstructor.subst(nopIop)

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645 { "code": "MiscDest = Op1",
646 "predicate_test": predicateTest },
647 ["IsSerializeAfter","IsNonSpeculative"])
648 header_output += RegRegOpDeclare.subst(mcr15UserIop)
649 decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
650 exec_output += PredOpExecute.subst(mcr15UserIop)
651
652 enterxCode = '''
641 FNPC = NPC | PcJBit | PcTBit;
653 ArmISA::PCState pc = PCS;
654 pc.nextThumb(true);
655 pc.nextJazelle(true);
656 PCS = pc;
642 '''
643 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
644 { "code": enterxCode,
645 "predicate_test": predicateTest }, [])
646 header_output += BasicDeclare.subst(enterxIop)
647 decoder_output += BasicConstructor.subst(enterxIop)
648 exec_output += PredOpExecute.subst(enterxIop)
649
650 leavexCode = '''
657 '''
658 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
659 { "code": enterxCode,
660 "predicate_test": predicateTest }, [])
661 header_output += BasicDeclare.subst(enterxIop)
662 decoder_output += BasicConstructor.subst(enterxIop)
663 exec_output += PredOpExecute.subst(enterxIop)
664
665 leavexCode = '''
651 FNPC = (NPC & ~PcJBit) | PcTBit;
666 ArmISA::PCState pc = PCS;
667 pc.nextThumb(true);
668 pc.nextJazelle(false);
669 PCS = pc;
652 '''
653 leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
654 { "code": leavexCode,
655 "predicate_test": predicateTest }, [])
656 header_output += BasicDeclare.subst(leavexIop)
657 decoder_output += BasicConstructor.subst(leavexIop)
658 exec_output += PredOpExecute.subst(leavexIop)
659

--- 96 unchanged lines hidden --- 		670 '''
671 leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
672 { "code": leavexCode,
673 "predicate_test": predicateTest }, [])
674 header_output += BasicDeclare.subst(leavexIop)
675 decoder_output += BasicConstructor.subst(leavexIop)
676 exec_output += PredOpExecute.subst(leavexIop)
677

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