misc.isa (7613:62159049ca81) misc.isa (7648:3e561a5c0456)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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485 if (SevMailbox)
486 SevMailbox = 0;
487 else
488 PseudoInst::quiesce(xc->tcBase());
489#endif
490 '''
491 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
492 { "code" : wfeCode, "predicate_test" : predicateTest },
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 476 unchanged lines hidden (view full) ---

485 if (SevMailbox)
486 SevMailbox = 0;
487 else
488 PseudoInst::quiesce(xc->tcBase());
489#endif
490 '''
491 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
492 { "code" : wfeCode, "predicate_test" : predicateTest },
493 ["IsNonSpeculative", "IsQuiesce"])
493 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
494 header_output += BasicDeclare.subst(wfeIop)
495 decoder_output += BasicConstructor.subst(wfeIop)
496 exec_output += PredOpExecute.subst(wfeIop)
497
498 wfiCode = '''
499#if FULL_SYSTEM
500 PseudoInst::quiesce(xc->tcBase());
501#endif

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512 System *sys = xc->tcBase()->getSystemPtr();
513 for (int x = 0; x < sys->numContexts(); x++) {
514 ThreadContext *oc = sys->getThreadContext(x);
515 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
516 }
517 '''
518 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
519 { "code" : sevCode, "predicate_test" : predicateTest },
494 header_output += BasicDeclare.subst(wfeIop)
495 decoder_output += BasicConstructor.subst(wfeIop)
496 exec_output += PredOpExecute.subst(wfeIop)
497
498 wfiCode = '''
499#if FULL_SYSTEM
500 PseudoInst::quiesce(xc->tcBase());
501#endif

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512 System *sys = xc->tcBase()->getSystemPtr();
513 for (int x = 0; x < sys->numContexts(); x++) {
514 ThreadContext *oc = sys->getThreadContext(x);
515 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
516 }
517 '''
518 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
519 { "code" : sevCode, "predicate_test" : predicateTest },
520 ["IsNonSpeculative", "IsQuiesce"])
520 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
521 header_output += BasicDeclare.subst(sevIop)
522 decoder_output += BasicConstructor.subst(sevIop)
523 exec_output += PredOpExecute.subst(sevIop)
524
525 itIop = InstObjParams("it", "ItInst", "PredOp", \
526 { "code" : "Itstate = machInst.newItstate;",
521 header_output += BasicDeclare.subst(sevIop)
522 decoder_output += BasicConstructor.subst(sevIop)
523 exec_output += PredOpExecute.subst(sevIop)
524
525 itIop = InstObjParams("it", "ItInst", "PredOp", \
526 { "code" : "Itstate = machInst.newItstate;",
527 "predicate_test" : predicateTest })
527 "predicate_test" : predicateTest },
528 ["IsNonSpeculative", "IsSerializeAfter"])
528 header_output += BasicDeclare.subst(itIop)
529 decoder_output += BasicConstructor.subst(itIop)
530 exec_output += PredOpExecute.subst(itIop)
531 unknownCode = '''
532#if FULL_SYSTEM
533 return new UndefinedInstruction;
534#else
535 return new UndefinedInstruction(machInst, true);

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658
659 setendCode = '''
660 CPSR cpsr = Cpsr;
661 cpsr.e = imm;
662 Cpsr = cpsr;
663 '''
664 setendIop = InstObjParams("setend", "Setend", "ImmOp",
665 { "code": setendCode,
529 header_output += BasicDeclare.subst(itIop)
530 decoder_output += BasicConstructor.subst(itIop)
531 exec_output += PredOpExecute.subst(itIop)
532 unknownCode = '''
533#if FULL_SYSTEM
534 return new UndefinedInstruction;
535#else
536 return new UndefinedInstruction(machInst, true);

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659
660 setendCode = '''
661 CPSR cpsr = Cpsr;
662 cpsr.e = imm;
663 Cpsr = cpsr;
664 '''
665 setendIop = InstObjParams("setend", "Setend", "ImmOp",
666 { "code": setendCode,
666 "predicate_test": predicateTest }, [])
667 "predicate_test": predicateTest },
668 ["IsSerializeAfter","IsNonSpeculative"])
667 header_output += ImmOpDeclare.subst(setendIop)
668 decoder_output += ImmOpConstructor.subst(setendIop)
669 exec_output += PredOpExecute.subst(setendIop)
670
671 clrexCode = '''
672 unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
673 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
674 '''

--- 78 unchanged lines hidden --- 		669 header_output += ImmOpDeclare.subst(setendIop)
670 decoder_output += ImmOpConstructor.subst(setendIop)
671 exec_output += PredOpExecute.subst(setendIop)
672
673 clrexCode = '''
674 unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
675 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
676 '''

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