misc.isa (7420:498b27bc326d) misc.isa (7422:feddb9077def)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 49 unchanged lines hidden (view full) ---

58
59let {{
60
61 header_output = decoder_output = exec_output = ""
62
63 mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
64 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
65 { "code": mrsCpsrCode,
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 49 unchanged lines hidden (view full) ---

58
59let {{
60
61 header_output = decoder_output = exec_output = ""
62
63 mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
64 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
65 { "code": mrsCpsrCode,
66 "predicate_test": predicateTest }, [])
66 "predicate_test": condPredicateTest }, [])
67 header_output += MrsDeclare.subst(mrsCpsrIop)
68 decoder_output += MrsConstructor.subst(mrsCpsrIop)
69 exec_output += PredOpExecute.subst(mrsCpsrIop)
70
71 mrsSpsrCode = "Dest = Spsr"
72 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
73 { "code": mrsSpsrCode,
74 "predicate_test": predicateTest }, [])

--- 5 unchanged lines hidden (view full) ---

80 SCTLR sctlr = Sctlr;
81 uint32_t newCpsr =
82 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
83 Cpsr = ~CondCodesMask & newCpsr;
84 CondCodes = CondCodesMask & newCpsr;
85 '''
86 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
87 { "code": msrCpsrRegCode,
67 header_output += MrsDeclare.subst(mrsCpsrIop)
68 decoder_output += MrsConstructor.subst(mrsCpsrIop)
69 exec_output += PredOpExecute.subst(mrsCpsrIop)
70
71 mrsSpsrCode = "Dest = Spsr"
72 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
73 { "code": mrsSpsrCode,
74 "predicate_test": predicateTest }, [])

--- 5 unchanged lines hidden (view full) ---

80 SCTLR sctlr = Sctlr;
81 uint32_t newCpsr =
82 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
83 Cpsr = ~CondCodesMask & newCpsr;
84 CondCodes = CondCodesMask & newCpsr;
85 '''
86 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
87 { "code": msrCpsrRegCode,
88 "predicate_test": predicateTest }, [])
88 "predicate_test": condPredicateTest }, [])
89 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
90 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
91 exec_output += PredOpExecute.subst(msrCpsrRegIop)
92
93 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
94 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
95 { "code": msrSpsrRegCode,
96 "predicate_test": predicateTest }, [])

--- 5 unchanged lines hidden (view full) ---

102 SCTLR sctlr = Sctlr;
103 uint32_t newCpsr =
104 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
105 Cpsr = ~CondCodesMask & newCpsr;
106 CondCodes = CondCodesMask & newCpsr;
107 '''
108 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
109 { "code": msrCpsrImmCode,
89 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
90 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
91 exec_output += PredOpExecute.subst(msrCpsrRegIop)
92
93 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
94 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
95 { "code": msrSpsrRegCode,
96 "predicate_test": predicateTest }, [])

--- 5 unchanged lines hidden (view full) ---

102 SCTLR sctlr = Sctlr;
103 uint32_t newCpsr =
104 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
105 Cpsr = ~CondCodesMask & newCpsr;
106 CondCodes = CondCodesMask & newCpsr;
107 '''
108 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
109 { "code": msrCpsrImmCode,
110 "predicate_test": predicateTest }, [])
110 "predicate_test": condPredicateTest }, [])
111 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
112 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
113 exec_output += PredOpExecute.subst(msrCpsrImmIop)
114
115 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
116 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
117 { "code": msrSpsrImmCode,
118 "predicate_test": predicateTest }, [])

--- 73 unchanged lines hidden (view full) ---

192 if (satInt(res, operand, imm))
193 CondCodes = CondCodes | (1 << 27);
194 else
195 CondCodes = CondCodes;
196 Dest = res;
197 '''
198 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
199 { "code": ssatCode,
111 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
112 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
113 exec_output += PredOpExecute.subst(msrCpsrImmIop)
114
115 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
116 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
117 { "code": msrSpsrImmCode,
118 "predicate_test": predicateTest }, [])

--- 73 unchanged lines hidden (view full) ---

192 if (satInt(res, operand, imm))
193 CondCodes = CondCodes | (1 << 27);
194 else
195 CondCodes = CondCodes;
196 Dest = res;
197 '''
198 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
199 { "code": ssatCode,
200 "predicate_test": predicateTest }, [])
200 "predicate_test": condPredicateTest }, [])
201 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
202 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
203 exec_output += PredOpExecute.subst(ssatIop)
204
205 usatCode = '''
206 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
207 int32_t res;
208 if (uSatInt(res, operand, imm))
209 CondCodes = CondCodes | (1 << 27);
210 else
211 CondCodes = CondCodes;
212 Dest = res;
213 '''
214 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
215 { "code": usatCode,
201 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
202 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
203 exec_output += PredOpExecute.subst(ssatIop)
204
205 usatCode = '''
206 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
207 int32_t res;
208 if (uSatInt(res, operand, imm))
209 CondCodes = CondCodes | (1 << 27);
210 else
211 CondCodes = CondCodes;
212 Dest = res;
213 '''
214 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
215 { "code": usatCode,
216 "predicate_test": predicateTest }, [])
216 "predicate_test": condPredicateTest }, [])
217 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
218 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
219 exec_output += PredOpExecute.subst(usatIop)
220
221 ssat16Code = '''
222 int32_t res;
223 uint32_t resTemp = 0;
224 CondCodes = CondCodes;

--- 4 unchanged lines hidden (view full) ---

229 replaceBits(resTemp, 15, 0, res);
230 if (satInt(res, argHigh, imm))
231 CondCodes = CondCodes | (1 << 27);
232 replaceBits(resTemp, 31, 16, res);
233 Dest = resTemp;
234 '''
235 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
236 { "code": ssat16Code,
217 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
218 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
219 exec_output += PredOpExecute.subst(usatIop)
220
221 ssat16Code = '''
222 int32_t res;
223 uint32_t resTemp = 0;
224 CondCodes = CondCodes;

--- 4 unchanged lines hidden (view full) ---

229 replaceBits(resTemp, 15, 0, res);
230 if (satInt(res, argHigh, imm))
231 CondCodes = CondCodes | (1 << 27);
232 replaceBits(resTemp, 31, 16, res);
233 Dest = resTemp;
234 '''
235 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
236 { "code": ssat16Code,
237 "predicate_test": predicateTest }, [])
237 "predicate_test": condPredicateTest }, [])
238 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
239 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
240 exec_output += PredOpExecute.subst(ssat16Iop)
241
242 usat16Code = '''
243 int32_t res;
244 uint32_t resTemp = 0;
245 CondCodes = CondCodes;

--- 4 unchanged lines hidden (view full) ---

250 replaceBits(resTemp, 15, 0, res);
251 if (uSatInt(res, argHigh, imm))
252 CondCodes = CondCodes | (1 << 27);
253 replaceBits(resTemp, 31, 16, res);
254 Dest = resTemp;
255 '''
256 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
257 { "code": usat16Code,
238 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
239 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
240 exec_output += PredOpExecute.subst(ssat16Iop)
241
242 usat16Code = '''
243 int32_t res;
244 uint32_t resTemp = 0;
245 CondCodes = CondCodes;

--- 4 unchanged lines hidden (view full) ---

250 replaceBits(resTemp, 15, 0, res);
251 if (uSatInt(res, argHigh, imm))
252 CondCodes = CondCodes | (1 << 27);
253 replaceBits(resTemp, 31, 16, res);
254 Dest = resTemp;
255 '''
256 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
257 { "code": usat16Code,
258 "predicate_test": predicateTest }, [])
258 "predicate_test": condPredicateTest }, [])
259 header_output += RegImmRegOpDeclare.subst(usat16Iop)
260 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
261 exec_output += PredOpExecute.subst(usat16Iop)
262
263 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
264 { "code":
265 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
266 "predicate_test": predicateTest }, [])

--- 143 unchanged lines hidden (view full) ---

410 replaceBits(resTemp, high, low,
411 bits(CondCodes, 16 + i) ?
412 bits(Op1, high, low) : bits(Op2, high, low));
413 }
414 Dest = resTemp;
415 '''
416 selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
417 { "code": selCode,
259 header_output += RegImmRegOpDeclare.subst(usat16Iop)
260 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
261 exec_output += PredOpExecute.subst(usat16Iop)
262
263 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
264 { "code":
265 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
266 "predicate_test": predicateTest }, [])

--- 143 unchanged lines hidden (view full) ---

410 replaceBits(resTemp, high, low,
411 bits(CondCodes, 16 + i) ?
412 bits(Op1, high, low) : bits(Op2, high, low));
413 }
414 Dest = resTemp;
415 '''
416 selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
417 { "code": selCode,
418 "predicate_test": predicateTest }, [])
418 "predicate_test": condPredicateTest }, [])
419 header_output += RegRegRegOpDeclare.subst(selIop)
420 decoder_output += RegRegRegOpConstructor.subst(selIop)
421 exec_output += PredOpExecute.subst(selIop)
422
423 usad8Code = '''
424 uint32_t resTemp = 0;
425 for (unsigned i = 0; i < 4; i++) {
426 int low = i * 8;

--- 268 unchanged lines hidden --- 		419 header_output += RegRegRegOpDeclare.subst(selIop)
420 decoder_output += RegRegRegOpConstructor.subst(selIop)
421 exec_output += PredOpExecute.subst(selIop)
422
423 usad8Code = '''
424 uint32_t resTemp = 0;
425 for (unsigned i = 0; i < 4; i++) {
426 int low = i * 8;

--- 268 unchanged lines hidden ---