misc.isa (7347:baefb46b29b2) | misc.isa (7400:f6c9b27c4dbe) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 63 unchanged lines hidden (view full) --- 72 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 73 { "code": mrsSpsrCode, 74 "predicate_test": predicateTest }, []) 75 header_output += MrsDeclare.subst(mrsSpsrIop) 76 decoder_output += MrsConstructor.subst(mrsSpsrIop) 77 exec_output += PredOpExecute.subst(mrsSpsrIop) 78 79 msrCpsrRegCode = ''' | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 63 unchanged lines hidden (view full) --- 72 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 73 { "code": mrsSpsrCode, 74 "predicate_test": predicateTest }, []) 75 header_output += MrsDeclare.subst(mrsSpsrIop) 76 decoder_output += MrsConstructor.subst(mrsSpsrIop) 77 exec_output += PredOpExecute.subst(mrsSpsrIop) 78 79 msrCpsrRegCode = ''' |
80 SCTLR sctlr = Sctlr; |
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80 uint32_t newCpsr = | 81 uint32_t newCpsr = |
81 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false); | 82 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); |
82 Cpsr = ~CondCodesMask & newCpsr; 83 CondCodes = CondCodesMask & newCpsr; 84 ''' 85 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 86 { "code": msrCpsrRegCode, 87 "predicate_test": predicateTest }, []) 88 header_output += MsrRegDeclare.subst(msrCpsrRegIop) 89 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 90 exec_output += PredOpExecute.subst(msrCpsrRegIop) 91 92 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 93 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 94 { "code": msrSpsrRegCode, 95 "predicate_test": predicateTest }, []) 96 header_output += MsrRegDeclare.subst(msrSpsrRegIop) 97 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 98 exec_output += PredOpExecute.subst(msrSpsrRegIop) 99 100 msrCpsrImmCode = ''' | 83 Cpsr = ~CondCodesMask & newCpsr; 84 CondCodes = CondCodesMask & newCpsr; 85 ''' 86 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 87 { "code": msrCpsrRegCode, 88 "predicate_test": predicateTest }, []) 89 header_output += MsrRegDeclare.subst(msrCpsrRegIop) 90 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 91 exec_output += PredOpExecute.subst(msrCpsrRegIop) 92 93 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 94 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 95 { "code": msrSpsrRegCode, 96 "predicate_test": predicateTest }, []) 97 header_output += MsrRegDeclare.subst(msrSpsrRegIop) 98 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 99 exec_output += PredOpExecute.subst(msrSpsrRegIop) 100 101 msrCpsrImmCode = ''' |
102 SCTLR sctlr = Sctlr; |
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101 uint32_t newCpsr = | 103 uint32_t newCpsr = |
102 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false); | 104 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); |
103 Cpsr = ~CondCodesMask & newCpsr; 104 CondCodes = CondCodesMask & newCpsr; 105 ''' 106 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 107 { "code": msrCpsrImmCode, 108 "predicate_test": predicateTest }, []) 109 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 110 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) --- 461 unchanged lines hidden (view full) --- 572 cpsCode = ''' 573 uint32_t mode = bits(imm, 4, 0); 574 uint32_t f = bits(imm, 5); 575 uint32_t i = bits(imm, 6); 576 uint32_t a = bits(imm, 7); 577 bool setMode = bits(imm, 8); 578 bool enable = bits(imm, 9); 579 CPSR cpsr = Cpsr; | 105 Cpsr = ~CondCodesMask & newCpsr; 106 CondCodes = CondCodesMask & newCpsr; 107 ''' 108 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 109 { "code": msrCpsrImmCode, 110 "predicate_test": predicateTest }, []) 111 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 112 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) --- 461 unchanged lines hidden (view full) --- 574 cpsCode = ''' 575 uint32_t mode = bits(imm, 4, 0); 576 uint32_t f = bits(imm, 5); 577 uint32_t i = bits(imm, 6); 578 uint32_t a = bits(imm, 7); 579 bool setMode = bits(imm, 8); 580 bool enable = bits(imm, 9); 581 CPSR cpsr = Cpsr; |
582 SCTLR sctlr = Sctlr; |
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580 if (cpsr.mode != MODE_USER) { 581 if (enable) { 582 if (f) cpsr.f = 0; 583 if (i) cpsr.i = 0; 584 if (a) cpsr.a = 0; 585 } else { | 583 if (cpsr.mode != MODE_USER) { 584 if (enable) { 585 if (f) cpsr.f = 0; 586 if (i) cpsr.i = 0; 587 if (a) cpsr.a = 0; 588 } else { |
586 if (f) cpsr.f = 1; | 589 if (f && !sctlr.nmfi) cpsr.f = 1; |
587 if (i) cpsr.i = 1; 588 if (a) cpsr.a = 1; 589 } 590 if (setMode) { 591 cpsr.mode = mode; 592 } 593 } 594 Cpsr = cpsr; 595 ''' 596 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 597 { "code": cpsCode, 598 "predicate_test": predicateTest }, []) 599 header_output += ImmOpDeclare.subst(cpsIop) 600 decoder_output += ImmOpConstructor.subst(cpsIop) 601 exec_output += PredOpExecute.subst(cpsIop) 602}}; | 590 if (i) cpsr.i = 1; 591 if (a) cpsr.a = 1; 592 } 593 if (setMode) { 594 cpsr.mode = mode; 595 } 596 } 597 Cpsr = cpsr; 598 ''' 599 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 600 { "code": cpsCode, 601 "predicate_test": predicateTest }, []) 602 header_output += ImmOpDeclare.subst(cpsIop) 603 decoder_output += ImmOpConstructor.subst(cpsIop) 604 exec_output += PredOpExecute.subst(cpsIop) 605}}; |