| misc.isa (7226:dd34f566bbca) | misc.isa (7232:f633e1a3f644) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 143 unchanged lines hidden (view full) --- 152 "predicate_test": predicateTest }, []) 153 header_output += RevOpDeclare.subst(revshIop) 154 decoder_output += RevOpConstructor.subst(revshIop) 155 exec_output += PredOpExecute.subst(revshIop) 156 157 ssatCode = ''' 158 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 159 int32_t res; | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 143 unchanged lines hidden (view full) --- 152 "predicate_test": predicateTest }, []) 153 header_output += RevOpDeclare.subst(revshIop) 154 decoder_output += RevOpConstructor.subst(revshIop) 155 exec_output += PredOpExecute.subst(revshIop) 156 157 ssatCode = ''' 158 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 159 int32_t res; |
| 160 if (satInt(res, operand, satImm)) | 160 if (satInt(res, operand, imm)) |
| 161 CondCodes = CondCodes | (1 << 27); 162 else 163 CondCodes = CondCodes; 164 Dest = res; 165 ''' | 161 CondCodes = CondCodes | (1 << 27); 162 else 163 CondCodes = CondCodes; 164 Dest = res; 165 ''' |
| 166 ssatIop = InstObjParams("ssat", "Ssat", "SatShiftOp", | 166 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", |
| 167 { "code": ssatCode, 168 "predicate_test": predicateTest }, []) | 167 { "code": ssatCode, 168 "predicate_test": predicateTest }, []) |
| 169 header_output += SatShiftOpDeclare.subst(ssatIop) 170 decoder_output += SatShiftOpConstructor.subst(ssatIop) | 169 header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 170 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) |
| 171 exec_output += PredOpExecute.subst(ssatIop) 172 173 usatCode = ''' 174 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 175 int32_t res; | 171 exec_output += PredOpExecute.subst(ssatIop) 172 173 usatCode = ''' 174 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 175 int32_t res; |
| 176 if (uSatInt(res, operand, satImm)) | 176 if (uSatInt(res, operand, imm)) |
| 177 CondCodes = CondCodes | (1 << 27); 178 else 179 CondCodes = CondCodes; 180 Dest = res; 181 ''' | 177 CondCodes = CondCodes | (1 << 27); 178 else 179 CondCodes = CondCodes; 180 Dest = res; 181 ''' |
| 182 usatIop = InstObjParams("usat", "Usat", "SatShiftOp", | 182 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", |
| 183 { "code": usatCode, 184 "predicate_test": predicateTest }, []) | 183 { "code": usatCode, 184 "predicate_test": predicateTest }, []) |
| 185 header_output += SatShiftOpDeclare.subst(usatIop) 186 decoder_output += SatShiftOpConstructor.subst(usatIop) | 185 header_output += RegImmRegShiftOpDeclare.subst(usatIop) 186 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) |
| 187 exec_output += PredOpExecute.subst(usatIop) 188 189 ssat16Code = ''' 190 int32_t res; 191 uint32_t resTemp = 0; 192 CondCodes = CondCodes; 193 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 194 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); | 187 exec_output += PredOpExecute.subst(usatIop) 188 189 ssat16Code = ''' 190 int32_t res; 191 uint32_t resTemp = 0; 192 CondCodes = CondCodes; 193 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 194 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); |
| 195 if (satInt(res, argLow, satImm)) | 195 if (satInt(res, argLow, imm)) |
| 196 CondCodes = CondCodes | (1 << 27); 197 replaceBits(resTemp, 15, 0, res); | 196 CondCodes = CondCodes | (1 << 27); 197 replaceBits(resTemp, 15, 0, res); |
| 198 if (satInt(res, argHigh, satImm)) | 198 if (satInt(res, argHigh, imm)) |
| 199 CondCodes = CondCodes | (1 << 27); 200 replaceBits(resTemp, 31, 16, res); 201 Dest = resTemp; 202 ''' | 199 CondCodes = CondCodes | (1 << 27); 200 replaceBits(resTemp, 31, 16, res); 201 Dest = resTemp; 202 ''' |
| 203 ssat16Iop = InstObjParams("ssat16", "Ssat16", "SatOp", | 203 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", |
| 204 { "code": ssat16Code, 205 "predicate_test": predicateTest }, []) | 204 { "code": ssat16Code, 205 "predicate_test": predicateTest }, []) |
| 206 header_output += SatOpDeclare.subst(ssat16Iop) 207 decoder_output += SatOpConstructor.subst(ssat16Iop) | 206 header_output += RegImmRegOpDeclare.subst(ssat16Iop) 207 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) |
| 208 exec_output += PredOpExecute.subst(ssat16Iop) 209 210 usat16Code = ''' 211 int32_t res; 212 uint32_t resTemp = 0; 213 CondCodes = CondCodes; 214 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 215 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); | 208 exec_output += PredOpExecute.subst(ssat16Iop) 209 210 usat16Code = ''' 211 int32_t res; 212 uint32_t resTemp = 0; 213 CondCodes = CondCodes; 214 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 215 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); |
| 216 if (uSatInt(res, argLow, satImm)) | 216 if (uSatInt(res, argLow, imm)) |
| 217 CondCodes = CondCodes | (1 << 27); 218 replaceBits(resTemp, 15, 0, res); | 217 CondCodes = CondCodes | (1 << 27); 218 replaceBits(resTemp, 15, 0, res); |
| 219 if (uSatInt(res, argHigh, satImm)) | 219 if (uSatInt(res, argHigh, imm)) |
| 220 CondCodes = CondCodes | (1 << 27); 221 replaceBits(resTemp, 31, 16, res); 222 Dest = resTemp; 223 ''' | 220 CondCodes = CondCodes | (1 << 27); 221 replaceBits(resTemp, 31, 16, res); 222 Dest = resTemp; 223 ''' |
| 224 usat16Iop = InstObjParams("usat16", "Usat16", "SatOp", | 224 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", |
| 225 { "code": usat16Code, 226 "predicate_test": predicateTest }, []) | 225 { "code": usat16Code, 226 "predicate_test": predicateTest }, []) |
| 227 header_output += SatOpDeclare.subst(usat16Iop) 228 decoder_output += SatOpConstructor.subst(usat16Iop) | 227 header_output += RegImmRegOpDeclare.subst(usat16Iop) 228 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) |
| 229 exec_output += PredOpExecute.subst(usat16Iop) 230}}; | 229 exec_output += PredOpExecute.subst(usat16Iop) 230}}; |