misc.isa (12789:b28b286fa57d) misc.isa (13999:a26c2e234a80)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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915 decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop)
916 exec_output += PredOpExecute.subst(mcr14Iop)
917
918 mrc15code = '''
919 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
920 MiscRegIndex miscReg = (MiscRegIndex)
921 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
922 preFlatOp1)).index();
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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915 decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop)
916 exec_output += PredOpExecute.subst(mcr14Iop)
917
918 mrc15code = '''
919 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
920 MiscRegIndex miscReg = (MiscRegIndex)
921 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
922 preFlatOp1)).index();
923 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
924 Hcptr, imm);
923
924 bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
925
925 bool can_read, undefined;
926 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
927 // if we're in non secure PL1 mode then we can trap regargless of whether
928 // the register is accessable, in other modes we trap if only if the register
929 // IS accessable.
930 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
931 !inSecureState(Scr, Cpsr)))) {
932 return std::make_shared<UndefinedInstruction>(machInst, false,

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947 exec_output += PredOpExecute.subst(mrc15Iop)
948
949
950 mcr15code = '''
951 int preFlatDest = snsBankedIndex(dest, xc->tcBase());
952 MiscRegIndex miscReg = (MiscRegIndex)
953 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
954 preFlatDest)).index();
926 bool can_read, undefined;
927 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
928 // if we're in non secure PL1 mode then we can trap regargless of whether
929 // the register is accessable, in other modes we trap if only if the register
930 // IS accessable.
931 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
932 !inSecureState(Scr, Cpsr)))) {
933 return std::make_shared<UndefinedInstruction>(machInst, false,

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948 exec_output += PredOpExecute.subst(mrc15Iop)
949
950
951 mcr15code = '''
952 int preFlatDest = snsBankedIndex(dest, xc->tcBase());
953 MiscRegIndex miscReg = (MiscRegIndex)
954 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
955 preFlatDest)).index();
955 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
956 Hcptr, imm);
956
957 bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
958
957 bool can_write, undefined;
958 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
959
960 // if we're in non secure PL1 mode then we can trap regargless of whether
961 // the register is accessable, in other modes we trap if only if the register
962 // IS accessable.
963 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
964 !inSecureState(Scr, Cpsr)))) {

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1087 header_output += BasicDeclare.subst(clrexIop)
1088 decoder_output += BasicConstructor.subst(clrexIop)
1089 exec_output += PredOpExecute.subst(clrexIop)
1090
1091 McrDcCheckCode = '''
1092 int preFlatDest = snsBankedIndex(dest, xc->tcBase());
1093 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
1094 RegId(MiscRegClass, preFlatDest)).index();
959 bool can_write, undefined;
960 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
961
962 // if we're in non secure PL1 mode then we can trap regargless of whether
963 // the register is accessable, in other modes we trap if only if the register
964 // IS accessable.
965 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
966 !inSecureState(Scr, Cpsr)))) {

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1089 header_output += BasicDeclare.subst(clrexIop)
1090 decoder_output += BasicConstructor.subst(clrexIop)
1091 exec_output += PredOpExecute.subst(clrexIop)
1092
1093 McrDcCheckCode = '''
1094 int preFlatDest = snsBankedIndex(dest, xc->tcBase());
1095 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
1096 RegId(MiscRegClass, preFlatDest)).index();
1095 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
1096 Hcptr, imm);
1097
1098 bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
1099
1097 bool can_write, undefined;
1098 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
1099
1100 // if we're in non secure PL1 mode then we can trap regardless
1101 // of whether the register is accessible, in other modes we
1102 // trap if only if the register IS accessible.
1103 if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
1104 !inSecureState(Scr, Cpsr)))) {

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1185 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop)
1186 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop)
1187 exec_output += Mcr15Execute.subst(McrDccimvacIop) + \
1188 Mcr15InitiateAcc.subst(McrDccimvacIop) + \
1189 Mcr15CompleteAcc.subst(McrDccimvacIop)
1190
1191 isbCode = '''
1192 // If the barrier is due to a CP15 access check for hyp traps
1100 bool can_write, undefined;
1101 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
1102
1103 // if we're in non secure PL1 mode then we can trap regardless
1104 // of whether the register is accessible, in other modes we
1105 // trap if only if the register IS accessible.
1106 if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
1107 !inSecureState(Scr, Cpsr)))) {

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1188 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop)
1189 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop)
1190 exec_output += Mcr15Execute.subst(McrDccimvacIop) + \
1191 Mcr15InitiateAcc.subst(McrDccimvacIop) + \
1192 Mcr15CompleteAcc.subst(McrDccimvacIop)
1193
1194 isbCode = '''
1195 // If the barrier is due to a CP15 access check for hyp traps
1193 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr,
1194 Hdcr, Hstr, Hcptr, imm)) {
1196 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB,
1197 xc->tcBase(), imm)) {
1195 return std::make_shared<HypervisorTrap>(machInst, imm,
1196 EC_TRAPPED_CP15_MCR_MRC);
1197 }
1198 '''
1199 isbIop = InstObjParams("isb", "Isb", "ImmOp",
1200 {"code": isbCode,
1201 "predicate_test": predicateTest},
1202 ['IsSquashAfter'])
1203 header_output += ImmOpDeclare.subst(isbIop)
1204 decoder_output += ImmOpConstructor.subst(isbIop)
1205 exec_output += PredOpExecute.subst(isbIop)
1206
1207 dsbCode = '''
1208 // If the barrier is due to a CP15 access check for hyp traps
1198 return std::make_shared<HypervisorTrap>(machInst, imm,
1199 EC_TRAPPED_CP15_MCR_MRC);
1200 }
1201 '''
1202 isbIop = InstObjParams("isb", "Isb", "ImmOp",
1203 {"code": isbCode,
1204 "predicate_test": predicateTest},
1205 ['IsSquashAfter'])
1206 header_output += ImmOpDeclare.subst(isbIop)
1207 decoder_output += ImmOpConstructor.subst(isbIop)
1208 exec_output += PredOpExecute.subst(isbIop)
1209
1210 dsbCode = '''
1211 // If the barrier is due to a CP15 access check for hyp traps
1209 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr,
1210 Hdcr, Hstr, Hcptr, imm)) {
1212 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB,
1213 xc->tcBase(), imm)) {
1211 return std::make_shared<HypervisorTrap>(machInst, imm,
1212 EC_TRAPPED_CP15_MCR_MRC);
1213 }
1214 '''
1215 dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
1216 {"code": dsbCode,
1217 "predicate_test": predicateTest},
1218 ['IsMemBarrier', 'IsSerializeAfter'])
1219 header_output += ImmOpDeclare.subst(dsbIop)
1220 decoder_output += ImmOpConstructor.subst(dsbIop)
1221 exec_output += PredOpExecute.subst(dsbIop)
1222
1223 dmbCode = '''
1224 // If the barrier is due to a CP15 access check for hyp traps
1214 return std::make_shared<HypervisorTrap>(machInst, imm,
1215 EC_TRAPPED_CP15_MCR_MRC);
1216 }
1217 '''
1218 dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
1219 {"code": dsbCode,
1220 "predicate_test": predicateTest},
1221 ['IsMemBarrier', 'IsSerializeAfter'])
1222 header_output += ImmOpDeclare.subst(dsbIop)
1223 decoder_output += ImmOpConstructor.subst(dsbIop)
1224 exec_output += PredOpExecute.subst(dsbIop)
1225
1226 dmbCode = '''
1227 // If the barrier is due to a CP15 access check for hyp traps
1225 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr,
1226 Hdcr, Hstr, Hcptr, imm)) {
1228 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB,
1229 xc->tcBase(), imm)) {
1227 return std::make_shared<HypervisorTrap>(machInst, imm,
1228 EC_TRAPPED_CP15_MCR_MRC);
1229 }
1230 '''
1231 dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
1232 {"code": dmbCode,
1233 "predicate_test": predicateTest},
1234 ['IsMemBarrier'])

--- 46 unchanged lines hidden --- 		1230 return std::make_shared<HypervisorTrap>(machInst, imm,
1231 EC_TRAPPED_CP15_MCR_MRC);
1232 }
1233 '''
1234 dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
1235 {"code": dmbCode,
1236 "predicate_test": predicateTest},
1237 ['IsMemBarrier'])

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