misc.isa (12560:9df712bd8c2f) misc.isa (12646:3fa08822f79c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 861 unchanged lines hidden (view full) ---

870 if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
871 Hstr, Hcptr, imm)) {
872 return std::make_shared<HypervisorTrap>(machInst, imm,
873 EC_TRAPPED_CP14_MCR_MRC);
874 }
875 Dest = MiscOp1;
876 '''
877
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 861 unchanged lines hidden (view full) ---

870 if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
871 Hstr, Hcptr, imm)) {
872 return std::make_shared<HypervisorTrap>(machInst, imm,
873 EC_TRAPPED_CP14_MCR_MRC);
874 }
875 Dest = MiscOp1;
876 '''
877
878 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp",
878 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp",
879 { "code": mrc14code,
880 "predicate_test": predicateTest }, [])
879 { "code": mrc14code,
880 "predicate_test": predicateTest }, [])
881 header_output += RegRegImmOpDeclare.subst(mrc14Iop)
882 decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
881 header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop)
882 decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop)
883 exec_output += PredOpExecute.subst(mrc14Iop)
884
885
886 mcr14code = '''
887 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
888 RegId(MiscRegClass, dest)).index();
889 bool can_write, undefined;
890 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
891 if (undefined || !can_write) {
892 return std::make_shared<UndefinedInstruction>(machInst, false,
893 mnemonic);
894 }
895 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
896 Hstr, Hcptr, imm)) {
897 return std::make_shared<HypervisorTrap>(machInst, imm,
898 EC_TRAPPED_CP14_MCR_MRC);
899 }
900 MiscDest = Op1;
901 '''
883 exec_output += PredOpExecute.subst(mrc14Iop)
884
885
886 mcr14code = '''
887 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
888 RegId(MiscRegClass, dest)).index();
889 bool can_write, undefined;
890 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
891 if (undefined || !can_write) {
892 return std::make_shared<UndefinedInstruction>(machInst, false,
893 mnemonic);
894 }
895 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
896 Hstr, Hcptr, imm)) {
897 return std::make_shared<HypervisorTrap>(machInst, imm,
898 EC_TRAPPED_CP14_MCR_MRC);
899 }
900 MiscDest = Op1;
901 '''
902 mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp",
902 mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp",
903 { "code": mcr14code,
904 "predicate_test": predicateTest },
905 ["IsSerializeAfter","IsNonSpeculative"])
903 { "code": mcr14code,
904 "predicate_test": predicateTest },
905 ["IsSerializeAfter","IsNonSpeculative"])
906 header_output += RegRegImmOpDeclare.subst(mcr14Iop)
907 decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
906 header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop)
907 decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop)
908 exec_output += PredOpExecute.subst(mcr14Iop)
909
910 mrc15code = '''
911 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
912 MiscRegIndex miscReg = (MiscRegIndex)
913 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
914 preFlatOp1)).index();
915 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,

--- 357 unchanged lines hidden --- 		908 exec_output += PredOpExecute.subst(mcr14Iop)
909
910 mrc15code = '''
911 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
912 MiscRegIndex miscReg = (MiscRegIndex)
913 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
914 preFlatOp1)).index();
915 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,

--- 357 unchanged lines hidden ---